A differential delay between a non-inverted output and an inverted output of a transistor circuit is reduced.

A transistor circuit includes a first transistor and a second transistor. The first transistor receives an input signal as an input, and outputs a first output signal. The second transistor receives the input signal as an input, and outputs a second output signal, which is in a reverse polarity with respect to the first output signal, on the basis of a bias that causes the second transistor to operate in a complementary manner with respect to the first transistor. The first transistor may include a first terminal, a second terminal, and a first control terminal that controls a current that flows between the first terminal and the second terminal. The second transistor may include a third terminal, a fourth terminal, and a second control terminal that controls a current that flows between the third terminal and the fourth terminal. The first output signal may be output from the first terminal, the second output signal may be output from the third terminal, and the input signal may be input to the second terminal of the first transistor and the second control terminal of the second transistor.

Systems and methods for load current compensation for analog input buffers. In various embodiments, an input buffer may include a first transistor (Q.sub.1) having a collector terminal coupled to a power supply node and a base terminal coupled to a first input node (v.sub.inp); a second transistor (Q.sub.2) having a collector terminal coupled to an emitter terminal of the first transistor (Q.sub.1); a third transistor (Q.sub.3) having an emitter terminal coupled to an emitter terminal of the second transistor (Q.sub.2) and to a ground node, a collector terminal coupled to a current source (I.sub.bias), and a base terminal coupled the collector terminal and to a base terminal of the second transistor (Q.sub.2); and a capacitor (C.sub.1) coupled to the base terminals of the second and third transistors (Q.sub.2 and Q.sub.3) and to a second input node (v.sub.inn), wherein the first and second input nodes (v.sub.inp and v.sub.inn) are differential inputs.