A communication device is disclosed. The disclosed communication device comprises: a transmission circuit for generating a transmission signal by using a first field effect transistor (FET) and a signal inputted from a first control circuit, and transmitting the transmission signal to a second control circuit; and a reception circuit for generating a reception signal by using a second field effect transistor (FET) and a signal received from the second control circuit, and outputting the reception signal to the first control circuit.

A communication device is disclosed. The disclosed communication device comprises: a transmission circuit for generating a transmission signal by using a first field effect transistor (FET) and a signal inputted from a first control circuit, and transmitting the transmission signal to a second control circuit; and a reception circuit for generating a reception signal by using a second field effect transistor (FET) and a signal received from the second control circuit, and outputting the reception signal to the first control circuit.

A communication device is disclosed. The disclosed communication device comprises: a transmission circuit for generating a transmission signal by using a first field effect transistor (FET) and a signal inputted from a first control circuit, and transmitting the transmission signal to a second control circuit; and a reception circuit for generating a reception signal by using a second field effect transistor (FET) and a signal received from the second control circuit, and outputting the reception signal to the first control circuit.

An apparatus comprising a first voltage domain circuit including a first circuit component configured to provide a first digital output signal; a second voltage domain circuit comprising a second circuit component; a level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal based thereon with an increased voltage level of the high state, and provide said second digital output signal to the second circuit component; wherein the level shifter arrangement comprises at least one stage, the at least one stage comprising an arrangement of one or more diode-connected PMOS transistors, coupled to a CMOS inverter arrangement; the CMOS inverter arrangement of a first of the at least one stages configured to receive the first digital output signal and the CMOS inverter arrangement of a final stage of the at least one stages configured to output said second digital output signal.

An apparatus comprising a first voltage domain circuit including a first circuit component configured to provide a first digital output signal; a second voltage domain circuit comprising a second circuit component; a level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal based thereon with an increased voltage level of the high state, and provide said second digital output signal to the second circuit component; wherein the level shifter arrangement comprises at least one stage, the at least one stage comprising an arrangement of one or more diode-connected PMOS transistors, coupled to a CMOS inverter arrangement; the CMOS inverter arrangement of a first of the at least one stages configured to receive the first digital output signal and the CMOS inverter arrangement of a final stage of the at least one stages configured to output said second digital output signal.

For a single input/output circuit, changing an input/output form is enabled by a simple configuration. In the input/output circuit, a circuit section includes power supply terminals and ground terminals. A switching section is switchable between a first state in which a power supply line and a ground line are coupled to one of the power supply terminals and one of the ground terminals and a second state in which the power supply line and the ground line are coupled to the other one of the power supply terminals and the other one of the ground terminals. The circuit section operates as a circuit corresponding to one of an open collector output and an open emitter output in the first state and operates as a circuit corresponding to the other one of the open collector output and the open emitter output in the second state.

For a single input/output circuit, changing an input/output form is enabled by a simple configuration. In the input/output circuit, a circuit section includes power supply terminals and ground terminals. A switching section is switchable between a first state in which a power supply line and a ground line are coupled to one of the power supply terminals and one of the ground terminals and a second state in which the power supply line and the ground line are coupled to the other one of the power supply terminals and the other one of the ground terminals. The circuit section operates as a circuit corresponding to one of an open collector output and an open emitter output in the first state and operates as a circuit corresponding to the other one of the open collector output and the open emitter output in the second state.

A level shifter according to some embodiments is disclosed. In some embodiments, a level shifter includes a middle-of-the-line (MOL) capacitor; and a circuit including at least one thin-film transistor coupled to the MOL capacitor, wherein an input voltage provided to the MOL capacitor is split between the MOL capacitor and the circuit. The MOL capacitor can be formed with a contact strip adjacent to a gate structure. A method of forming a level shifter using thin-oxide technologies includes forming a middle-of-the-line (MOL) capacitor; forming a circuit with one or more thin-film transistors; and coupling the MOL capacitor to the circuit such that an input voltage provided at the MOL capacitor is split between the MOL capacitor and the circuit.

The invention relates to a level converter for adjusting a first reference potential and/or a first communication voltage of a first component to a second reference potential and/or a second communication voltage of a second component, wherein the level converter is arranged between the first component and the second component, wherein the level converter has a first transistor with a downstream first resistor, wherein the level converter is configured in such a way that the second reference potential drops at the first resistor in a blocked state of the first transistor and that the second communication voltage drops at the first resistor in an open state of the first transistor.

A power supply device includes an output circuit configured to be supplied with electric power from a power supply, and to output a current, a driving circuit configured to control an output operation of the output circuit to output a current, an overcurrent detection circuit configured to output a detection signal to a first node when detecting an overcurrent in the output circuit, an off-state fixing circuit configured to output an off-state fixing signal to the driving circuit for performing a forcible suspension of the output operation of the output circuit based on a detection signal inputted to the first node, regardless of whether a control signal is outputted, and a control unit configured to receive the detection signal and to output the control signal for controlling the output operation to the driving circuit in order to cause the driving circuit to control the output operation.