A common gate input circuit for III/V D-mode Buffered FET Logic (BFL) maximizes the dynamic range to drive a level shift section to set the proper voltage levels to switch the BFL and allows for decoupling of the switch point from the dynamic range. A common gate switching section includes a D-mode FET (FET1) configured as a load and a D-mode FET (FET2) configured as a common gate connected in series between high and low supplies Vdd and Vee1 (typically ground potential). The gate electrode of FET2 is coupled to Vee1 and the source electrode of FET2 is driven by the external digital signals. This eliminates the additional supply Vss, thus maximizing the dynamic range of the section to switch between Vdd and Vee1 and decouples the dynamic range from the switch point. An input level shift section may shift the Data In to the source electrode of FET2 to shift the switch point and to present a high input impedance.

Disclosed are a circuit and a system which prevent unnecessary power consumption by cutting off static current occurring when a signal is transmitted from an integrated circuit with a low power supply voltage to an integrated circuit with a high power supply voltage.

A GaN logic circuit may include an input node receiving an input voltage, a first pull up transistor pulling up an output voltage in response to the input voltage, and a first depletion mode transistor having a first gate to which a first gate voltage is applied and a second gate to which a second gate voltage is applied. The first depletion mode transistor may control the first pull up transistor in response to a gate voltage difference between the first gate voltage and the second gate voltage. The logic device may further include a capacitor having a first end coupled to the first depletion mode transistor and a second end coupled to the first pull up transistor.

A signal transmission device for transmitting a pulse signal to drive a switching element includes: a first external terminal configured to receive a first input pulse signal for ordinary driving; a second external terminal configured to receive a second input pulse signal for forcible driving; and a first logic configured to generate a driving pulse signal according to the first and second input pulse signals. The first logic gives priority to the second input pulse signal over the first input pulse signal.

A GaN logic circuit may include an input node receiving an input voltage, a first pull up transistor pulling up an output voltage in response to the input voltage, and a first depletion mode transistor having a first gate to which a first gate voltage is applied and a second gate to which a second gate voltage is applied. The first depletion mode transistor may control the first pull up transistor in response to a gate voltage difference between the first gate voltage and the second gate voltage. The logic device may further include a capacitor having a first end coupled to the first depletion mode transistor and a second end coupled to the first pull up transistor.

A signal transmission device for transmitting a pulse signal to drive a switching element includes: a first external terminal configured to receive a first input pulse signal for ordinary driving; a second external terminal configured to receive a second input pulse signal for forcible driving; and a first logic configured to generate a driving pulse signal according to the first and second input pulse signals. The first logic gives priority to the second input pulse signal over the first input pulse signal.

A signal transmission device is configured to transmit a pulse signal while isolating between a primary circuit system and secondary circuit system to drive a switching element. The signal transmission device includes: a first external terminal configured to receive a first input signal for driving a state of a driver output; a second external terminal configured to receive a second input signal for ASC operation; and a third external terminal configured to output the driver output and follow a logic level at the second external terminal.