A multiplexing circuit includes an output terminal, a first type transistor, a second type transistor and an impedance circuit. The output terminal is arranged to output a serial output signal. The first type transistor is coupled between a first reference voltage and the output terminal. The second type transistor is coupled between a second reference voltage and the output terminal, wherein the first type is different from the second type. The impedance circuit is arranged to provide an impedance between a gate terminal of the first type transistor and the output terminal.

Described is an apparatus which comprises: a reference device; and a processor having a plurality of circuit units, each circuit unit is operable to electronically couple with the reference device such that only one circuit unit of the plurality of circuit units is electronically coupled to the reference device at a given time while other circuit units of the plurality are electronically uncoupled to the reference device during that time.

The off-chip driving (OCD) device includes a signal transition detector, a front-end driver, a first main driver, a second main driver, a first resistance provider and a second resistance provider. The signal transition detector is used to detect a transition status of an input signal to generate decision information. The front-end driver generates control signals according to the decision information, and generates driving signals according to the input signal. The first main driver and the second main driver generate an output signal to a pad according to the driving signals. The first resistance provider adjusts a first resistance between the first main driver and the pad according to a first control signal. The second resistance provider adjusts a second resistance between the second main driver and the pad according to a second control signal.

A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.

An impedance calibration circuit includes a first leg set having an impedance calibrated to a first target impedance according to an impedance control code during an activation period of a first timing control signal, a second leg set having an impedance calibrated to a second target impedance according to the impedance control code during an activation period of a second timing control signal, a code generation circuit configured to calibrate and output a value of the impedance control code according to a result of comparing a voltage of a node, to which the first leg set is connected, with a reference voltage, and a timing control signal generation circuit configured to generate the first timing control signal and the second timing control signal having different activation periods in response to an impedance calibration enable signal.

An ultrasound imaging device includes a plurality of ultrasound transducers arranged in an array of rows and columns. Each of the transducers has a first electrode and a second electrode. The first electrodes of the transducers of a same row are interconnected and the second electrodes of the transducers of a same column are interconnected.

An input/output (I/O) interface includes a resistance-to-current (R/I) converter; an internal resistor; first, second, and third current sources; first and second diodes; and a comparator. The R/I converter is coupled to an I/O pin and generates an output current based on an external resistance at the I/O pin during an analog operating mode. The internal resistor is coupled to the I/O pin and to ground. The first current source is coupled to the R/I converter circuit. The first diode is coupled to the R/I converter and to the I/O pin. The second current source is coupled to the R/I converter and the first diode and to ground. The second diode is coupled to the I/O pin and to the third current source. The comparator has inputs coupled to the I/O pin and to a reference voltage, and outputs a control signal indicative of a digital operating mode.

A method of handling signal transmission applicable to a display system includes a plurality of steps. The steps include transmitting a reset signal embedded in a first data signal to each of at least one source driver via a first data channel, generating a first control signal for setting the at least one source driver, and transmitting the first control signal embedded in a second data signal to each of the at least one source driver via a second data channel when the reset signal is transmitted via the first data channel.

A low voltage differential signal driver includes an output driver including an N-channel source follower, a P-channel source follower, and a plurality of differential switching circuits, a plurality of high-potential output control circuits to control a terminal of the N-channel source follower of the output driver to make a high-potential output of the differential output from the output driver have a prescribed value, a plurality of low-potential output control circuits to control a terminal of the P-channel source follower of the output driver to make a low-potential output of the differential output from the output driver have a prescribed value, a high-potential generation circuit used in common for the plurality of high-potential output control circuits, and a low-potential generation circuit used in common for the plurality of low-potential output control circuits. The output driver outputs a differential output, and one of the plurality of high-potential output control circuits.

A multiplexing circuit includes an output terminal, a first type transistor, a second type transistor and an impedance circuit. The output terminal is arranged to output a serial output signal. The first type transistor is coupled between a first reference voltage and the output terminal. The second type transistor is coupled between a second reference voltage and the output terminal, wherein the first type is different from the second type. The impedance circuit is arranged to provide an impedance between a gate terminal of the first type transistor and the output terminal.