An OR-gate device includes two cross shaped structures, each cross shaped structure includes a channel. Where at an end of each channel is an ohmic contact connecting the two cross shaped structures. Each cross shaped structure includes an epitaxial layer including a III-N heterostructure such as InAlN/GaN. Wherein an amount of an In concentration of the InAlN/GaN is tuned to lattice match with GaN, resulting in electron mobility to generate ballistic electrons. A fin structure located in the channel includes a gate formed transversely to a longitudinal axis of the channel. The gate is controlled using a voltage over the fin structure. Wherein the fin structure is formed to induce an energy-field structure that shifts by an amount of the voltage to control an opening of the gate that the flow of ballistic electrons is passing through, which in turn changes a depletion width, subjecting the ballistic electrons to interference.

Disclosed is a semiconductor logic element having a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries with the described logic element.

Disclosed is a semiconductor logic element having a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries with the described logic element.

Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.

Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.

A gate driver includes a drive signal input terminal, a drive signal output terminal, a gate drive circuit, and a serial communication interface. The drive signal input terminal is configured to receive a gate drive signal. The gate drive circuit is coupled to the drive signal input terminal and the drive signal output terminal. The gate drive circuit is configured to provide the gate drive signal to the drive signal output terminal. The serial communication interface is coupled to the drive signal input terminal.

A gate driver includes a drive signal input terminal, a drive signal output terminal, a gate drive circuit, and a serial communication interface. The drive signal input terminal is configured to receive a gate drive signal. The gate drive circuit is coupled to the drive signal input terminal and the drive signal output terminal. The gate drive circuit is configured to provide the gate drive signal to the drive signal output terminal. The serial communication interface is coupled to the drive signal input terminal.

Disclosed is a semiconductor logic element having a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries with the described logic element.

Disclosed is a semiconductor logic element having a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries with the described logic element.

A gate driver includes a drive signal input terminal, a drive signal output terminal, a gate drive circuit, and a serial communication interface. The drive signal input terminal is configured to receive a gate drive signal. The gate drive circuit is coupled to the drive signal input terminal and the drive signal output terminal. The gate drive circuit is configured to provide the gate drive signal to the drive signal output terminal. The serial communication interface is coupled to the drive signal input terminal.