Aspects of the present disclosure control aging of a signal path in an idle mode to mitigate aging. In one example, an input of the signal path is alternately parked low and high over multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, a clock signal (e.g., a clock signal with a low frequency) is input to the signal path during idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, the input of the signal path is parked high or low during each idle period based on an aging pattern.

A switched current source circuit, comprising first and second voltage source nodes; a load; a current source; and capacitor switching circuitry comprising a load node, a capacitor and a plurality of switches configured, based on a control signal, to adopt a biasing configuration followed by an active configuration, wherein in the biasing configuration, the load node is conductively connected to the second voltage source node to bias a voltage level at the load node, and the capacitor is connected so that it at least partly charges; and in the active configuration, the load node is conductively connected via the load to the first voltage source node, and via the capacitor to the current source to increase a potential difference between the first voltage source node and the load node.

A switched current source circuit, comprising first and second voltage source nodes; a load; a current source; and capacitor switching circuitry comprising a load node, a capacitor and a plurality of switches configured, based on a control signal, to adopt a biasing configuration followed by an active configuration, wherein in the biasing configuration, the load node is conductively connected to the second voltage source node to bias a voltage level at the load node, and the capacitor is connected so that it at least partly charges; and in the active configuration, the load node is conductively connected via the load to the first voltage source node, and via the capacitor to the current source to increase a potential difference between the first voltage source node and the load node.

In an embodiment an integrated device includes a first physical unclonable function module configured to generate an initial data group and management module configured to generate an output data group from at least the initial data group, authorize only D successive deliveries of the output data group on a first output interface of the device, D being a non-zero positive integer, and prevent any new generation of the output data group.

A method, a unit and circuits for implementing Boolean logics based on computing-in-memory transistors. The method is implemented by using the characteristics and the read-write mode of the computing-in-memory transistor; the basic unit consists of a computing-in-memory transistor and a pull resistor; the pull resistor in the basic unit is connected in series with the transistor, and the gate of the transistor is independent; the basic units can implement sixteen Boolean logic operations through different circuit structures and voltage configuration schemes. Compared with the logic circuit structure of the conventional CMOS transistors, the present disclosure can implement more logic operations with fewer transistors, which greatly optimizes circuit density and computing speed caused by data transmission between storage units and process units.

A method, a unit and circuits for implementing Boolean logics based on computing-in-memory transistors. The method is implemented by using the characteristics and the read-write mode of the computing-in-memory transistor; the basic unit consists of a computing-in-memory transistor and a pull resistor; the pull resistor in the basic unit is connected in series with the transistor, and the gate of the transistor is independent; the basic units can implement sixteen Boolean logic operations through different circuit structures and voltage configuration schemes. Compared with the logic circuit structure of the conventional CMOS transistors, the present disclosure can implement more logic operations with fewer transistors, which greatly optimizes circuit density and computing speed caused by data transmission between storage units and process units.

Semiconductor devices includes third arms. A channel from the first and second arms extends to a channel of the third arm. When a current from a first voltage is flowing from the first arm to the second arm, a flow of ballistic electrons is generated that flow through the third arm channel from the channel of the first and second arms to the third arm channel. A fin structure located in the third arm channel and includes a gate. The gate is controlled using a second voltage over the fin structure, the fin structure is formed to induce an energy-field structure that shifts by an amount of the second voltage to control an opening of the gate that the flow of ballistic electrons pass through, which in turn changes a depletion width, subjecting the ballistic electrons to diffraction, and then interference.

A ternary logic circuit includes: a first inverter unit; a second inverter unit arranged in parallel with the first inverter unit; a first junction unit arranged between the first inverter unit and an output terminal and including a tunnel PN junction; and a second junction unit arranged between the second inverter unit and the output terminal and including a tunnel PN junction, wherein, when an absolute value of an input voltage applied to an input terminal is less than a first input voltage, the output terminal outputs a first output voltage, and when the absolute value of the input voltage is greater than the first input voltage and less than a second input voltage, the output terminal outputs a second output voltage, and when the absolute value of the input terminal is greater than the second input voltage, the output terminal outputs a third output voltage.

A ternary logic circuit includes: a first inverter unit; a second inverter unit arranged in parallel with the first inverter unit; a first junction unit arranged between the first inverter unit and an output terminal and including a tunnel PN junction; and a second junction unit arranged between the second inverter unit and the output terminal and including a tunnel PN junction, wherein, when an absolute value of an input voltage applied to an input terminal is less than a first input voltage, the output terminal outputs a first output voltage, and when the absolute value of the input voltage is greater than the first input voltage and less than a second input voltage, the output terminal outputs a second output voltage, and when the absolute value of the input terminal is greater than the second input voltage, the output terminal outputs a third output voltage.

A Controller Area Network (CAN) transceiver determines a voltage differential signal from analog signaling and provides a digital output signal at a receiver output to a CAN controller based on the voltage differential signal. The analog signaling received from the CAN bus can operate with a first voltage level scheme of a first CAN protocol and a second voltage level scheme for a second CAN protocol. A first comparator compares the voltage differential signal to a first threshold which is set to a value which differentiates between a logic low bit and logic high bit in accordance with the second CAN protocol. Filtering circuitry selectively filters an output of the first comparator based on detection of noise on the CAN bus to provide a first digital signal indicative of activity on the CAN bus according to the second CAN protocol.