Methods, systems, and devices for die location detection for grouped memory dies are described. A memory device may include multiple memory die that are coupled with a shared bus. In some examples, each memory die may include a circuit configured to output an identifier associated with a location of the respective memory die. For example, a first memory die may output a first identifier, based on receiving one or more signals, that identifies a location of the first memory die. Identifying the locations of the respective memory dies may allow for the dies to be individually accessed despite being coupled with a shared bus.

A method for providing more than one function to pins of a programmable device used in a server system includes the programmable device and first and second devices. The programmable device is electrically connected to the first device and the second device. The programmable device includes a major logic communication device, a detection module, a storage module, and at least one multiplexing pin. The second device is powered on, sending an in-position signal to the detection module through the at least one multiplexing pin. The detection module transmits the in-position signal to the storage module. The major logic communication module communicates with the first device through the at least one multiplexing pin. A system applying the method are also disclosed.

An integrated circuit (IC) for clock and phase aligning and synchronization between physical (PHY) layers and a communications controller is provided. The IC includes a clock multiplier configured to multiply a frequency of the clock signal from a plurality of PHY layers to match a frequency of a clock signal of the controller, wherein the clock signal from the plurality of PHY layers is less than the frequency of the clock signal of the controller. IC support circuitry is configured to provide the multiplied clock signal to the controller. The IC includes a first clock divider configured to divide the frequency of the multiplied clock signal and to output the divided clock signal to the controller. The IC includes a phase alignment circuit configured to align phases of one or more data signals based on a phase of the clock signal and a phase of the multiplied clock signal.

Technologies for providing shared memory for accelerator sleds includes an accelerator sled to receive, with a memory controller, a memory access request from an accelerator device to access a region of memory. The request is to identify the region of memory with a logical address. Additionally, the accelerator sled is to determine from a map of logical addresses and associated physical address, the physical address associated with the region of memory. In addition, the accelerator sled is to route the memory access request to a memory device associated with the determined physical address.

A sequencer for use with a countermeasure defense system includes an input signal indicative of firing an expendable, a circuit card that receives the input signal indicative of firing the expendable and an output analog signal from the circuit card that fires the expendable. The parameters of the output analog signal correspond to parameters of a digital waveform.

A sequencer for use with a countermeasure defense system includes an input signal indicative of firing an expendable, a circuit card that receives the input signal indicative of firing the expendable and an output analog signal from the circuit card that fires the expendable. The parameters of the output analog signal correspond to parameters of a digital waveform.

The present disclosure describes a power supply switch that includes a voltage generator, a switch circuit, and a confirmation circuit. The voltage generator is configured to compare a first power supply voltage to a second power supply voltage and to output the first power supply voltage or the second power supply voltage as a bulk voltage (V.sub.bulk). The switch circuit includes one or more transistors and is configured to (i) bias bulk terminals of the one or more transistors with the V.sub.bulk and (ii) output either the first power supply voltage or the second power supply voltage as a voltage output signal. The confirmation circuit is configured to output a confirmation signal that indicates whether the voltage output signal transitioned from the first power supply voltage to the second power supply voltage.

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.

Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect. The interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor as data packets.

Provided are a method of dynamically configuring a FPGA and a network security device. The network security device includes a CPU and at least one FPGA coupled with the CPU. The CPU generates a configuration entry for a target FPGA in response to a user instruction. The configuration entry includes a classification number and a configuration content for the target FPGA. The CPU sends the configuration entry to each FPGA coupled with the CPU, Each FPGA obtains its own classification number, compares its own classification number with the classification number in the configuration entry, and stores the configuration content when the own classification number the same with the classification number in the configuration entry.