An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Each row includes a word line drive circuit powered by an adaptive supply voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit generates the adaptive supply voltage for powering the word line drive circuits during the simultaneous actuation. A level of the adaptive supply voltage is modulated dependent on integrated circuit process and/or temperature conditions in order to optimize word line underdrive performance and inhibit unwanted memory cell data flip.

An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Each row includes a word line drive circuit powered by an adaptive supply voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit generates the adaptive supply voltage for powering the word line drive circuits during the simultaneous actuation. A level of the adaptive supply voltage is modulated dependent on integrated circuit process and/or temperature conditions in order to optimize word line underdrive performance and inhibit unwanted memory cell data flip.

Various techniques are provided to implement look-up table (LUT) circuits. In one example, a LUT circuit includes a first LUT configured to selectively receive a first input signal and each input signal of a set of input signals and determine a first output signal based on the first input signal and/or an input signal(s) of the set. The LUT circuit also includes a second LUT configured to selectively receive a second input signal and each input signal of the set and determine a second output signal based on the second input signal and/or an input signal(s) of the set. The LUT circuit also includes a multiplexer configured to selectively receive the first and second output signals and a third input signal, and selectively provide, based on the third input signal, the first or second output signal as an output of the LUT circuit. Related systems and methods are also provided.

Various techniques are provided to implement look-up table (LUT) circuits. In one example, a LUT circuit includes a first LUT configured to selectively receive a first input signal and each input signal of a set of input signals and determine a first output signal based on the first input signal and/or an input signal(s) of the set. The LUT circuit also includes a second LUT configured to selectively receive a second input signal and each input signal of the set and determine a second output signal based on the second input signal and/or an input signal(s) of the set. The LUT circuit also includes a multiplexer configured to selectively receive the first and second output signals and a third input signal, and selectively provide, based on the third input signal, the first or second output signal as an output of the LUT circuit. Related systems and methods are also provided.

Memory might include a controller configured to cause the memory to capacitively couple a first voltage level from a voltage node to a node of a sense circuit, selectively discharge the node of the sense circuit through a memory cell, measure a current demand of the voltage node while selectively discharging the node of the sense circuit through the memory cell, determine a second voltage level in response to the measured current demand, isolate the node of the sense circuit from the memory cell, capacitively couple the second voltage level from the voltage node to the node of the sense circuit, and determine a data state of the memory cell in response to a voltage level of the node of the sense circuit while capacitively coupling the second voltage level to the node of the sense circuit.

Memory might include a controller configured to cause the memory to capacitively couple a first voltage level from a voltage node to a node of a sense circuit, selectively discharge the node of the sense circuit through a memory cell, measure a current demand of the voltage node while selectively discharging the node of the sense circuit through the memory cell, determine a second voltage level in response to the measured current demand, isolate the node of the sense circuit from the memory cell, capacitively couple the second voltage level from the voltage node to the node of the sense circuit, and determine a data state of the memory cell in response to a voltage level of the node of the sense circuit while capacitively coupling the second voltage level to the node of the sense circuit.

A method and system are directed to protecting hardware IP, particularly of ASIC designs. Programmability is introduced into an ASIC design to increase the difficulty of formulating ASIC designs as Boolean Satisfiability (SAT) problems. Fine-grain redaction of security-critical information from a design is employed by removing high-entropy logic blocks and subsequently inserting programmable components in place of the redacted portion to hide the actual design intent.

A method and system are directed to protecting hardware IP, particularly of ASIC designs. Programmability is introduced into an ASIC design to increase the difficulty of formulating ASIC designs as Boolean Satisfiability (SAT) problems. Fine-grain redaction of security-critical information from a design is employed by removing high-entropy logic blocks and subsequently inserting programmable components in place of the redacted portion to hide the actual design intent.

Systems and methods for analyzing applications (“apps”) on a mobile device for security risks for a company while maintaining the mobile device owner's privacy and confidentiality concerning the applications. The mobile device may be a user's personal device (a “bring your own device”). In an example method, a process generates one or more cryptographic representations of application information for each application on the mobile device. The cryptographic representations may comprise a hash or composite hash. The cryptographic representations may be transmit outside the mobile device to a system which makes a determination and provides an indication whether the application is permitted or not permitted for use at the company. The company can be associated with a hashed permitted or not permitted list. The application information can include application name, executable code, and a version number. The method may include automatically remediating the application if it matches a known risk.

Systems and methods for analyzing applications (“apps”) on a mobile device for security risks for a company while maintaining the mobile device owner's privacy and confidentiality concerning the applications. The mobile device may be a user's personal device (a “bring your own device”). In an example method, a process generates one or more cryptographic representations of application information for each application on the mobile device. The cryptographic representations may comprise a hash or composite hash. The cryptographic representations may be transmit outside the mobile device to a system which makes a determination and provides an indication whether the application is permitted or not permitted for use at the company. The company can be associated with a hashed permitted or not permitted list. The application information can include application name, executable code, and a version number. The method may include automatically remediating the application if it matches a known risk.