In some embodiments, a superconducting parametric amplification neural network (SPANN) includes neurons that operate in the analog domain, and a fanout network coupling the neurons that operates in the digital domain. Each neuron is provided one or more input currents having a resolution of several bits. The neuron weights the currents, sums the weighted currents with an optional bias or threshold current, then applies a nonlinear activation function to the result. The nonlinear function is implemented using a quantum flux parametron (QFP), thereby simultaneously amplifying and digitizing the output current signal. The digitized output of some or all neurons in each layer is provided to the next layer using a fanout network that operates to preserve the digital information held in the current.

One example describes a superconducting XOR-gate system. The system includes a pulse generator configured to generate a decision pulse. The system also includes an input superconducting XOR-2 gate that receives a first superconducting logic input signal and a second superconducting logic input signal and is configured to perform a logic XOR function based on the decision pulse on a given phase of a clock signal to provide an intermediate superconducting logic output signal. The system also includes an output superconducting XOR-2 gate that receives the intermediate superconducting logic output signal and a third superconducting logic input signal and is configured to perform a logic XOR function based on the decision pulse on the given phase of the clock signal to provide a superconducting logic output signal.

An electric circuit includes a plurality of superconducting components, each of the plurality of superconducting components having: a respective first terminal; a respective second terminal; and a respective input. The electric circuit further includes a bias current source electrically-connected to the respective first terminal of each of the plurality of superconducting components. The bias current source is configured to provide a bias current adapted to cause the electric circuit to function as a logical OR gate on the respective inputs of the plurality of superconducting components. The electric circuit further includes an output node adapted to output a state of the logical OR gate.

The present disclosure relates to improved electronic structures for propagating logic states between superconducting digital logic gates using a three-junction interferometer in a receiver circuit to reduce reflecting signals that otherwise result in distortions in the signals being transmitted between the gates. Other improved electronic structures comprise passive transmission lines (PTLs) with transmission line matching circuitry that has previously been avoided. The matching circuity minimizes generation and propagation of spurious pulses emitted by Josephson junctions used in the digital logic gates.

A circuit can include a first sub-circuit, a second sub-circuit, and a third sub-circuit. The first sub-circuit can store a reset state or a set state, and can include a first Josephson junction (JJ), a second JJ, and a third JJ coupled in parallel using superconducting inductors. The first JJ, the second JJ, and the third JJ can be biased using a JJ-based current source. The second sub-circuit can switch the first sub-circuit to the set state in response to receiving a pulse. The third sub-circuit can switch the first sub-circuit to the reset state in response to receiving one or more pulses.

Systems and methods are provided for applying flux to a quantum-coherent superconducting circuit. In one example, a system includes a long-Josephson junction (LJJ), an inductive loop coupled to the LJJ and inductively coupled to the quantum-coherent superconducting circuit, and a single flux quantum (SFQ) controller configured to apply a SFQ pulse to a first end of the LJJ that propagates the SFQ pulse to a second end of the LJJ, while also applying a flux quantum to the inductive loop resulting in a first value of control flux being applied to the quantum-coherent superconducting circuit.

A quantum computing devices includes: a qubit; a readout device coupled to the qubit, the readout device including a frequency filter having a filter frequency range; and an amplifier device coupled to the readout device, in which the amplifier device is configured to amplify a measurement signal from the readout device upon receiving a pump signal having a pump frequency that is outside of the filter frequency range of the frequency filter.

A superconducting device includes two nodes and a Josephson junction coupled between the two nodes, wherein the Josephson junction is characterized by a superconducting phase difference, φ, wherein the superconducting device has a potential that varies as a function of the superconducting phase difference, φ, and has a single potential well. The potential has a non-zero cubic term and quartic term is zero. The Josephson junction may be a single small Josephson junction. The superconducting device may include a superconducting ring connected between the two nodes. The superconducting ring may include a first ring portion with a plurality of large Josephson junctions connected in series. The superconducting ring may also include a second ring portion that includes the single small Josephson junction in parallel with the plurality of large Josephson junctions between the two nodes.

An electric circuit includes one or more photon detector components and a superconducting logic gate component coupled to respective outputs of the one or more photon detector components. The electric circuit further includes a bias source electrically coupled to the superconducting logic gate component, the bias source configured to provide a bias current adapted to cause the superconducting logic gate component to function as a logical gate. The electric circuit also includes an optical switch component electrically coupled to an output of the superconducting logic gate component.

An electric circuit includes a plurality of superconducting components, each of the plurality of superconducting components having: a respective first terminal; a respective second terminal; and a respective input. The electric circuit further includes a bias current source electrically-connected to the respective first terminal of each of the plurality of superconducting components. The bias current source is configured to provide a bias current adapted to cause the electric circuit to function as a logical OR gate on the respective inputs of the plurality of superconducting components. The electric circuit further includes an output node adapted to output a state of the logical OR gate.