Certain aspects of the present disclosure provide techniques for performing machine learning computations in a compute in memory (CIM) array comprising a plurality of bit cells, including: determining that a sparsity of input data to a machine learning model exceeds an input data sparsity threshold; disabling one or more bit cells in the CIM array based on the sparsity of the input data prior to processing the input data; processing the input data with bit cells not disabled in the CIM array to generate an output value; applying a compensation to the output value based on the sparsity to generate a compensated output value; and outputting the compensated output value.

A motor drive control device capable of determining a drive state of a motor is provided. The motor drive control device includes a plurality of motor drive circuits performing, based on drive control signals (Sca1 and Sca2) for controlling the number of rotations of a motor, control of energization of the motor and outputting FG signals (fg1 and fg2) having a cycle corresponding to the actual number of rotations of the motor, a composite signal generation circuit receiving an input of each of the FG signals output from the motor drive circuits and generating a composite signal by combining input signals, and a drive control circuit generating, based on a speed command signal indicating a target number of rotations of the motor, the drive control signals and outputting the drive control signals to each of the motor drive circuits. The FG signals output from the motor drive circuits have a phase difference from each other.

A motor drive control device capable of determining a drive state of a motor is provided. The motor drive control device includes a plurality of motor drive circuits performing, based on drive control signals (Sca1 and Sca2) for controlling the number of rotations of a motor, control of energization of the motor and outputting FG signals (fg1 and fg2) having a cycle corresponding to the actual number of rotations of the motor, a composite signal generation circuit receiving an input of each of the FG signals output from the motor drive circuits and generating a composite signal by combining input signals, and a drive control circuit generating, based on a speed command signal indicating a target number of rotations of the motor, the drive control signals and outputting the drive control signals to each of the motor drive circuits. The FG signals output from the motor drive circuits have a phase difference from each other.

The present disclosure relates to circuitry for performing a multiply-accumulate (MAC) operation. The circuitry comprises a first multiplexer having a plurality of inputs for receiving a plurality of unary-coded input signals representing operands of the MAC operation and an output for outputting a multiplexer output signal representing a result of the MAC operation and a first vector quantizer configured to receive a plurality of weighting signals, each representing a proportion of a computation time period for which a respective one of the unary-coded input signals should be selected by the multiplexer and to output a first selector signal to the multiplexer to cause the multiplexer to select each of the input signals in accordance with the plurality of weighting signals.

An aspect relates to a filter or a first gyrator including a first set of cascaded inverters, and a first set of one or more passive devices coupled to the first set of cascaded inverters. Another aspect relates to a method including applying an input signal to an input of a first one of a set of cascaded inverters coupled to a set of one or more passive devices, and receiving an output signal from the set of cascaded inverters, the output signal being a filtered version of the input signal. Still another aspect relates to a transceiver including a filter with a first set of cascaded inverters, and a first set of one or more passive devices coupled to the first set of cascaded inverters; and a mixer coupled to the filter.

An aspect relates to a filter or a first gyrator including a first set of cascaded inverters, and a first set of one or more passive devices coupled to the first set of cascaded inverters. Another aspect relates to a method including applying an input signal to an input of a first one of a set of cascaded inverters coupled to a set of one or more passive devices, and receiving an output signal from the set of cascaded inverters, the output signal being a filtered version of the input signal. Still another aspect relates to a transceiver including a filter with a first set of cascaded inverters, and a first set of one or more passive devices coupled to the first set of cascaded inverters; and a mixer coupled to the filter.

One embodiment of the present invention sets forth a data pipeline, which includes a first mousetrap element and a second mousetrap element in a first pipeline stage. Each mousetrap element includes a request latch that, when enabled, allows a request signal to pass from the first pipeline stage to a second pipeline stage following the first pipeline stage in the data pipeline. Each mousetrap element also includes a data latch that, when enabled, allows a data element to pass from the first pipeline stage to the second pipeline stage. Each mousetrap element further includes a latch controller that enables and disables the request and data latches based on a phase signal that alternates between a first value that configures the first mousetrap element to transmit data to the second pipeline stage and a second value that configures the second mousetrap element to transmit data to the second pipeline stage.

One embodiment of the present invention sets forth a data pipeline, which includes a first mousetrap element and a second mousetrap element in a first pipeline stage. Each mousetrap element includes a request latch that, when enabled, allows a request signal to pass from the first pipeline stage to a second pipeline stage following the first pipeline stage in the data pipeline. Each mousetrap element also includes a data latch that, when enabled, allows a data element to pass from the first pipeline stage to the second pipeline stage. Each mousetrap element further includes a latch controller that enables and disables the request and data latches based on a phase signal that alternates between a first value that configures the first mousetrap element to transmit data to the second pipeline stage and a second value that configures the second mousetrap element to transmit data to the second pipeline stage.

A retention flip-flop includes a master latch outputting a first signal which is generated based on a signal inputted through an input terminal based on first control signals; a slave latch outputting a second signal generated based on the first signal based on the first control signals and second control signals; and a control logic that generates the first control signals based on a clock signal and provides the first control signals to the master latch and the slave latch, and generates the second control signals based on a power down signal and provides the second control signals to the slave latch. The slave latch comprises a retention latch which transmits the first signal to an output terminal as the second signal by operating as an open loop based on the second control signals or maintains the second signal by forming a closed loop based on the second control signals.

Clock multiplexer circuitry outputs one of a first or second clock signal. First selection circuitry is connected in series with first counter circuitry. The first selection circuitry and the first counter circuitry receive a first clock signal and a first selection signal. A first control signal is generated based on the first clock signal and the first selection signal. Second selection circuitry is connected in series with second counter circuitry. The second selection circuitry and the second counter circuitry receive a second clock signal and a second selection signal. A second control signal is generated based on the second clock signal and the second selection signal. The output circuitry is connected to the first counter circuitry and the second counter circuitry. The output circuitry outputs one of the first clock signal and the second clock signal based on the first control signal and the second control signal.