Alternative data selector, a full adder, and a ripple carry adder are disclosed. The alternative data selector includes: a NOR logic circuit configured to receive a selection signal and an inverted first input and generate an intermediate result; and an AND-OR-NOT logic circuit configured to receive the selection signal, a second input, and the intermediate result of the NOR logic circuit and generate an inverted output.

Methods and apparatus of Exclusive OR (XOR) engine in a random access memory device to accelerate cryptographical operations in processors. For example, an integrated circuit memory device enclosed within a single integrated circuit package can include an XOR engine that is coupled with memory units in the random access memory device (e.g., having dynamic random access memory (DRAM) or non-volatile random access memory (NVRAM)). A processor (e.g., System-on-Chip (SoC) or Central Processing Unit (CPU)) can have encryption logic that performs cryptographical operations using XOR operations that are performed by the XOR engine in the random access memory device using the data in the random access memory device.

Methods and apparatus of Exclusive OR (XOR) engine in a random access memory device to accelerate cryptographical operations in processors. For example, an integrated circuit memory device enclosed within a single integrated circuit package can include an XOR engine that is coupled with memory units in the random access memory device (e.g., having dynamic random access memory (DRAM) or non-volatile random access memory (NVRAM)). A processor (e.g., System-on-Chip (SoC) or Central Processing Unit (CPU)) can have encryption logic that performs cryptographical operations using XOR operations that are performed by the XOR engine in the random access memory device using the data in the random access memory device.

The semiconductor device includes a magnetic switch provided to a semiconductor substrate. The magnetic switch includes: a horizontal Hall element including first electrodes and second electrodes arranged at positions perpendicular to the first electrodes; a switch circuit configured to select a drive current direction of the Hall element from four directions; an SH comparator configured to alternately perform a first operation for sampling a signal transmitted from the Hall element and a second operation for sending a signal which is based on a result of comparing a value of the sampled signal and a reference value; a latch circuit configured to hold this sent signal and send the held signal as a latch output signal; and a control circuit configured to select the drive current direction in each of a period for the first operation and a period for the second operation based on the latch output signal.

The semiconductor device includes a magnetic switch provided to a semiconductor substrate. The magnetic switch includes: a horizontal Hall element including first electrodes and second electrodes arranged at positions perpendicular to the first electrodes; a switch circuit configured to select a drive current direction of the Hall element from four directions; an SH comparator configured to alternately perform a first operation for sampling a signal transmitted from the Hall element and a second operation for sending a signal which is based on a result of comparing a value of the sampled signal and a reference value; a latch circuit configured to hold this sent signal and send the held signal as a latch output signal; and a control circuit configured to select the drive current direction in each of a period for the first operation and a period for the second operation based on the latch output signal.

A current load circuit for testing a power supply circuit includes a control circuit and a load generation circuit. The control circuit is configured to generate a reset signal according to a clock signal. The load generation circuit is coupled to the control circuit and has several load configurations. The load generation circuit is configured to provide one of the load configurations as a current load of the load generation circuit according to the clock signal and the reset signal and receive a portion of the supply current provided by the power supply circuit according to the current load to generate an indication signal for indicating a performance of the power supply circuit.

A current load circuit for testing a power supply circuit includes a control circuit and a load generation circuit. The control circuit is configured to generate a reset signal according to a clock signal. The load generation circuit is coupled to the control circuit and has several load configurations. The load generation circuit is configured to provide one of the load configurations as a current load of the load generation circuit according to the clock signal and the reset signal and receive a portion of the supply current provided by the power supply circuit according to the current load to generate an indication signal for indicating a performance of the power supply circuit.

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.

Disclosed is a low-power negative voltage generator for RF switches, which is provided with a monostable trigger and a voltage-controlled oscillator before a non-overlapping clock circuit and a charge pump. The monostable trigger can change from a stable state to a transient state when a switch channel selection signal jumps; the clock frequency of the voltage controlled oscillator will be increased during the transient state of the monostable trigger, and after the monostable trigger returns to a stable state, its clock frequency will be reduced to the initial state, thereby ensuring that the circuit power consumption is reduced while the transient characteristic is high.

Disclosed is a low-power negative voltage generator for RF switches, which is provided with a monostable trigger and a voltage-controlled oscillator before a non-overlapping clock circuit and a charge pump. The monostable trigger can change from a stable state to a transient state when a switch channel selection signal jumps; the clock frequency of the voltage controlled oscillator will be increased during the transient state of the monostable trigger, and after the monostable trigger returns to a stable state, its clock frequency will be reduced to the initial state, thereby ensuring that the circuit power consumption is reduced while the transient characteristic is high.