A DLL circuit that has a programmable output frequency is provided. The DLL circuit uses a single delay line to produce the multiple frequencies. In various embodiments, the delay line is configured to receive an input clock defining an input clock period. The delay line comprises delay stages, each configured to generate a corresponding output clock having a phase relative to the input clock based on a delay of the delay line. In those embodiments, a control circuit is configured to change the delay of the delay line so as to cause a phase difference between the input clock and a sensed output clock to be substantially equal to the input clock period. An edge combiner is configured to generate a DLL output clock based on the output clocks of the delay stages and presents an equal schematic load for each of the output clocks of the delay stages.

A power supply with duty cycle limiting circuit includes a conversion circuit, a drive circuit, a control unit, and a duty cycle limiting circuit. The duty cycle limiting circuit converts a control signal into a control voltage, and determines whether a power switch of a power supply is turned off according to the control voltage and a threshold voltage to limit a duty cycle of the power switch.

Exemplary embodiments may include a method of applying a charging pulse to an output capacitor, detecting satisfaction of a charging threshold, ending the charging pulse in response to the detecting the satisfaction of the charging threshold, and discharging the sampling capacitor in response to the detecting the satisfaction of the charging threshold. In some embodiments, once a sampling capacitor voltage drops below a discharging threshold, a charging pulse is applied. Exemplary embodiments may also include an apparatus with a controller coupled to an input node, a timer coupled to the controller, an inductive charger coupled to the controller, to an input node, and to an output node, and a sensor coupled to the controller and the output node. Exemplary embodiments may further include an apparatus where a sensor with a sampling capacitor has a first terminal coupled to the output node and a second terminal coupled to the controller and the inductive charger.

Methods and apparatuses are provided for temperature independent resistive-capacitive delay circuits of a semiconductor device. For example, delays associated with ZQ calibration or timing of the RAS chain may be implemented that to include circuitry that exhibits both proportional to absolute temperature (PTAT) characteristics and complementary to absolute temperature (CTAT) characteristics in order to control delay times across a range of operating temperatures. The RC delay circuits may include a first type of circuitry having impedance with PTAT characteristics that is coupled to an output node in parallel with a second type of circuitry having impedance with CTAT characteristics. The first type of circuitry may include a resistor and the second type of circuitry may include a transistor, in some embodiments.

A method of frequency doubling includes receiving a first clock that has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase; outputting a second clock using a multiplexer by selecting one of the first phase and the second phase of the first clock in accordance with a third clock; delaying the second clock into a fourth clock using a recirculating delay circuit; and using a divide-by-two circuit to output the third clock in accordance with the fourth clock.

Methods and apparatuses are provided for temperature independent resistive-capacitive delay circuits of a semiconductor device. For example, delays associated with ZQ calibration or timing of the RAS chain may be implemented that to include circuitry that exhibits both proportional to absolute temperature (PTAT) characteristics and complementary to absolute temperature (CTAT) characteristics in order to control delay times across a range of operating temperatures. The RC delay circuits may include a first type of circuitry having impedance with PTAT characteristics that is coupled to an output node in parallel with a second type of circuitry having impedance with CTAT characteristics. The first type of circuitry may include a resistor and the second type of circuitry may include a transistor, in some embodiments.

A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.

A device of correcting duty cycle includes: a duty cycle correcting circuit, a controller of the duty cycle correcting circuit and a duty cycle detecting circuit. The duty cycle correcting circuit generates a pair of phase-shifting clocks in accordance with a pair of complementary clocks and regenerates a regenerated clock in accordance with the pair of phase-shifting clocks. The controller of the duty cycle correcting circuit couples to the duty cycle correcting circuit. The duty cycle detecting circuit couples to the duty cycle correcting circuit and the controller of the duty cycle correcting circuit, and generates a detecting output to the controller of the duty cycle correcting circuit in accordance with a current duty cycle of the regenerated clock. The controller of the duty cycle correcting circuit controls the duty cycle correcting circuit in accordance with the detecting output to adjust the pair of phase-shifting clocks.

A device of correcting duty cycle includes: a duty cycle correcting circuit, a controller of the duty cycle correcting circuit and a duty cycle detecting circuit. The duty cycle correcting circuit generates a pair of phase-shifting clocks in accordance with a pair of complementary clocks and regenerates a regenerated clock in accordance with the pair of phase-shifting clocks. The controller of the duty cycle correcting circuit couples to the duty cycle correcting circuit. The duty cycle detecting circuit couples to the duty cycle correcting circuit and the controller of the duty cycle correcting circuit, and generates a detecting output to the controller of the duty cycle correcting circuit in accordance with a current duty cycle of the regenerated clock. The controller of the duty cycle correcting circuit controls the duty cycle correcting circuit in accordance with the detecting output to adjust the pair of phase-shifting clocks.

A method of frequency doubling includes receiving a first clock that has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase; outputting a second clock using a multiplexer by selecting one of the first phase and the second phase of the first clock in accordance with a third clock; delaying the second clock into a fourth clock using a recirculating delay circuit; and using a divide-by-two circuit to output the third clock in accordance with the fourth clock.