An output control circuit may include a period setting signal generation unit configured to output a setup signal enabled during a designated period, in response to a delayed locked loop (DLL) locking signal and an output enable reset signal. The output control circuit may also include a clock division unit configured to divide an internal clock at a preset division ratio in response to the setup signal, and output a divided clock. In addition, the output control circuit may include a shift unit configured to shift the setup signal by a preset first time in response to the divided clock, and output a first delayed setup signal. Further, the output control circuit may include an output unit configured to receive and process the first delayed setup signal in response to the divided clock, and output the output enable reset signal.

A circuit for reducing duty cycle distortion of a clock signal includes an amplifier configured to receive an input clock signal and generate an amplified clock signal. The circuit also includes a filter coupled to the amplifier and configured to generate a filtered clock signal based on the amplified clock signal. The circuit also includes a gating circuit coupled to the filter and configured to receive the filtered clock signal and selectively output the filter clock signal responsive to a first control signal. The circuit also includes a control circuit coupled to the gating circuit and the filter, where the control circuit is configured to receive a timing signal, receive an enable signal, and generate the first and a second control signal based on the timing and enable signals. The second control signal alters impedance of a feedback path of the filter.