A delay circuit is disclosed. The delay circuit is coupled to a relay switch that is contained in a power conversion device. When an electronic device having the power conversion device is operated in a sleep mode, the delay circuit applies a time delaying process to a power signal that is transmitted to the relay switch, such that a rising time of each of switch-on pulses contained by the power signal is delayed for a specific time. The specific time is set to be longer than a pulse width of each of power-on pulses contained by a power switching signal of the power conversion device. As such, when the electronic device is operated in the sleep mode, switching actions of the relay switch is properly controlled, thereby making the power conversion device not produce noise. Moreover, the service life of the relay unit is also extended.

The invention provides a clock delay adjusting circuit based on edge addition and an integrated chip thereof. The clock delay adjusting circuit comprises a clock delay unit, a weight coefficient unit and an edge addition unit, wherein the clock delay unit is used for conducting equal-interval delay on clock signals inputted into the input end of the clock delay unit to obtain and output at least three delay clock signals at equal intervals, the weight coefficient unit is used for generating weight signals with the number the same as the number of the delay clock signals according to digital codes inputted into the input end of the weight coefficient unit and outputting the weight signals, and the edge addition unit is used for receiving the delay clock signals and the weight signals, conducting weighted summation on the delay clock signals according to the weight signals and outputting signals obtained through weighted summation to obtain new clock signals with continuous clock rising edges/continuous clock falling edges, wherein the number of the new clock signals is the same as the number of the delay clock signals. In addition, the clock delay adjusting circuit can be made into the integrated chip. In view of the present invention, the problems that an existing clock delay adjusting circuit is low in adjustment accuracy and can not meet the requirement for high-precision time-share sampling are well solved.

A delay-adjusted digital-unit interface comprises a first node, a second node, a third node, and an amplifier assembly. The first node is connected to a pull-up resistor and can be connected to the signal line of a transmission line connected to a first digital unit at a distal point. The second node is configured to be connected to a second reference electrical potential, a signal-return line of the transmission line, and a signal-return line of a second digital unit. The third node can be connected to a signal line of the second digital unit. The amplifier assembly is configured to be connected between the first node and the third node, to transform between high electrical potentials on the first node and lower electrical potentials on the third node, and to diversely delay low-to-high and high-to-low signal transitions transmitted by the second digital unit during communication with the first digital unit.

The invention provides a clock delay adjusting circuit based on edge addition and an integrated chip thereof. The clock delay adjusting circuit comprises a clock delay unit, a weight coefficient unit and an edge addition unit, wherein the clock delay unit is used for conducting equal-interval delay on clock signals inputted into the input end of the clock delay unit to obtain and output at least three delay clock signals at equal intervals, the weight coefficient unit is used for generating weight signals with the number the same as the number of the delay clock signals according to digital codes inputted into the input end of the weight coefficient unit and outputting the weight signals, and the edge addition unit is used for receiving the delay clock signals and the weight signals, conducting weighted summation on the delay clock signals according to the weight signals and outputting signals obtained through weighted summation to obtain new clock signals with continuous clock rising edges/continuous clock falling edges, wherein the number of the new clock signals is the same as the number of the delay clock signals. In addition, the clock delay adjusting circuit can be made into the integrated chip. In view of the present invention, the problems that an existing clock delay adjusting circuit is low in adjustment accuracy and can not meet the requirement for high-precision time-share sampling are well solved.

A delay-adjusted digital-unit interface comprises a first node, a second node, a third node, and an amplifier assembly. The first node is connected to a pull-up resistor and can be connected to the signal line of a transmission line connected to a first digital unit at a distal point. The second node is configured to be connected to a second reference electrical potential, a signal-return line of the transmission line, and a signal-return line of a second digital unit. The third node can be connected to a signal line of the second digital unit. The amplifier assembly is configured to be connected between the first node and the third node, to transform between high electrical potentials on the first node and lower electrical potentials on the third node, and to diversely delay low-to-high and high-to-low signal transitions transmitted by the second digital unit during communication with the first digital unit.