The disclosed subject matter includes an apparatus. The apparatus is configured to provide an approximate differentiation of an input continuous-time signal. The apparatus includes a continuous-time delay block configured to receive the input continuous-time signal and to delay the input continuous-time signal by a predetermined delay factor to generate a delayed input continuous-time signal; a processing block configured to determine a difference between the input continuous-time signal and the delayed input continuous-time signal; and a multiplication block configured to multiply the difference by a multiplication factor to provide the approximate differentiation of the input continuous-time signal.

A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.

A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.

A monitoring circuit comprises a clock generator generating a first clock, a code generator generating an output code by varying a value of an input code in response to an input clock, receiving a feedback signal, and varying the value of the input code by performing set operations in a first mode and performing inverse set operations in a second mode, and an operation controller transmitting the first clock and a start code when the code generator enters the first mode, setting the output code as a counting code when the code generator exits from the first mode, transmitting a second clock and the counting code when the code generator enters the second mode, and counting a toggling number of the second clock in the second mode until the output code has a value identical with that of the start code.

A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

The invention relates to a time-delay circuit (1) for a digital signal (3), particularly for a clock signal, comprising:

an input (2) for the digital signal (3);
an oscillator (4) for generating an internal clock signal (5);
at least one delay channel (6) adding a certain delay to the digital input signal (3) based on the internal clock signal (5); and
an output (7) for a delayed digital signal (8).

In an embodiment, a circuit includes cascaded delay units arranged in a chain, each delay unit having an input-to-output delay time, wherein a first delay unit in the chain is configured to receive an input signal for propagating along the delay units in the chain, logic circuitry coupled to delay units in the chain, the logic circuitry configured to generate a clock signal as a logic combination of signals input to and output from the delay units in the chain and feedback circuitry configured to supply to the first delay unit in the chain a feedback signal, the feedback circuitry including a first feedback signal path from a last delay unit in the chain to the first delay unit in the chain and a second feedback signal path from an intermediate delay unit in the chain to the first delay unit in the chain, the intermediate delay unit arranged between the first delay unit in the chain and the last delay unit in the chain.

According to one embodiment, an information processing device, includes: a digital-to-pulse converter configured to output a pulse signal including a pulse with a pulse length corresponding to a digital input signal; and a bidirectional selective oscillator including a first ring oscillator and a second ring oscillator, the first ring oscillator including a plurality of delay elements connected in a ring shape in a first direction, the second ring oscillator including a plurality of delay elements connected in a ring shape in a second direction reverse to the first direction. The bidirectional selective oscillator is configured to select one of the first ring oscillator and the second ring oscillator depending on a sign of the digital input signal, oscillate the selected ring oscillator during a period when the pulse is outputted, and keep a state of oscillation operation when the pulse stops being outputted.

A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.