We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on the substrate. The second heterojunction transistor comprises: a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas; a third terminal operatively connected to the second III-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in the first dimension and operatively connected to the second III-nitride semiconductor region; a second gate region being formed over the second III-nitride semiconductor region, and between the third terminal and the fourth terminal. One of the first and second heterojunction transistors is an enhancement mode field effect transistor and the other of the first and second heterojunction transistors is a depletion mode field effect transistor.

A semiconductor device includes a junction field effect transistor (JFET) including a source electrode, a drain electrode, and a gate electrode, and a metal oxide semiconductor field effect transistor (MOSFET) including a source electrode, a drain electrode, and a gate electrode. The JFET and the MOSFET are cascode-connected such that the source electrode of the JFET and the drain electrode of the MOSFET are electrically connected. A gate voltage dependency of the JFET or a capacitance ratio of a mirror capacitance of the MOSFET to an input capacitance of the MOSFET is adjusted in a predetermined range.

A semiconductor device includes a MOSFET including a drift layer, a channel layer, a trench gate structure, a source layer, a drain layer, a source electrode, and a drain electrode. The trench gate structure includes a trench penetrating the channel layer and protruding into the drift layer, a gate insulating film disposed on a wall surface of the trench, and a gate electrode disposed on the gate insulating film. A portion of the trench protruding into the drift layer is entirely covered with a well layer, and the well layer is connected to the channel layer.

In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.

A rectifier circuit has one or more bridge circuits each with: a first leg with two diodes in series and an AC terminal at a midpoint between the two, a second leg with two semiconductor switches in parallel to the first, a third diode connected to a upper node of each leg, a fourth diode connected to a lower node of each leg, and a capacitor leg with two capacitors in series between the third and fourth diode. A midpoint between the capacitors is connected to a midpoint between the semiconductor switches. The first arrangement is two controllable semiconductor switches in series. A gate node of the second is connected to a first load terminal of the first switch and the first load terminal is connected to the lower node. The second semiconductor switch is a third controllable semiconductor switch with a gate node connected to the lower node.

Passive Ethernet by-pass switches, methods of using the same, and systems including the passive Ethernet by-pass switches include a first connection configured to be coupled to a first Ethernet port, a second connection configured to be coupled to a second Ethernet port, and switching circuitry including at least one internal switch operable to allow network communication between the first connection, the second connection, and at least one Ethernet controller, the at least one internal switch including a depletion mode transistor operable to bridge the first connection to the second connection to establish communication between the first connection and the second connection.

This disclosure relates to a discrete cascode semiconductor device and associated method of manufacture, the device includes: a high voltage depletion mode device die having gate, source and drain terminals arranged on a first major surface thereof; a low voltage enhancement mode device die having a gate and a source terminal formed on a first major surface thereof, and a drain terminal formed on a second major surface opposite the first major surface. The drain terminal of the high voltage device die is mounted on a drain connection; the source terminal of the low voltage device die and the gate terminal of the high voltage device are mounted on a common source connection; and the drain terminal of the low voltage device die is mounted on the source terminal of the high voltage device.

An integrated circuit may include a power transistor coupled between a supply pin and an output pin; a current sensing circuit configured to sense a load current passing through the power transistor and to provide a respective current sense signal; a first configuration pin; a current output circuit configured to provide a diagnosis current at a current output pin; a diagnosis pin for receiving a diagnosis request signal; and a control circuit configured to: select a characteristic curve representing a current versus time characteristic dependent on a external circuit connected to the first configuration pin; generate a drive signal for the power transistor dependent on the selected characteristic curve and the current sense signal; and control—dependent on a pulse pattern of the diagnosis request signal—the current output circuit to set the value of the diagnosis current such that it represents the load current or the selected characteristic curve.

A miniature circuit breaker for providing short circuit and overload protection is disclosed herein. The miniature circuit breaker features a field effect transistor (FET), which may be a depletion mode metal oxide semiconductor FET (D MOSFET), a junction field-effect transistor (JFET), or a silicon carbide JFET, the FET being connected to a bi-metallic switch, where the bi-metallic switch acts as a temperature sensing circuit breaker. In combination, the D MOSFET and bi-metallic switch are able to limit current to downstream circuit components, thus protecting the components from damage.

A switching circuit of a motor drive includes a high-side switch configured to selectively conduct current between a DC positive conductor and an output conductor, and a low-side switch configured to selectively conduct current between the output conductor and a DC negative conductor. The high-side switch comprises a depletion mode (D-Mode) gallium nitride (GaN) high-electron-mobility transistor (HEMT) and a Si-FET in a cascaded configuration, and the low-side switch comprises a D-Mode GaN HEMT. This arrangement can provide a safe state operation in which the switching circuit provides a default condition providing electrical continuity between the DC negative conductor and the output conductor and providing electrical isolation between the DC positive conductor and the output conductor in the event of a loss of control signals.