A system includes a pulse counter having a selectable pulse counter read-out rate, a pulse counter read-out (PCRO) storage register that stores a PCRO count, and a pulse-burst counter that has a pulse-burst counter read-out rate that is faster than all but the fastest selectable pulse counter read-out rate, a subtractor module in electronic communication with the pulse counter and the PCRO that subtracts the PCRO count from the pulse counter read-out count to output an uncorrected pulse count, a selection module in electronic communication with the pulse-burst counter that selects the pulse counter read-out rate in response to input from the pulse-burst counter, a multiplexer in electronic communication with the subtractor module and the selection module, the multiplexer selecting from among at least two dead-time correction transforms, the transform corresponding to the selected pulse counter read-out rate, and a control-and-readout module that outputs a dead-time corrected pulse rate.

A system includes a pulse counter having a selectable pulse counter read-out rate, a pulse counter read-out (PCRO) storage register that stores a PCRO count, and a pulse-burst counter that has a pulse-burst counter read-out rate that is faster than all but the fastest selectable pulse counter read-out rate, a subtractor module in electronic communication with the pulse counter and the PCRO that subtracts the PCRO count from the pulse counter read-out count to output an uncorrected pulse count, a selection module in electronic communication with the pulse-burst counter that selects the pulse counter read-out rate in response to input from the pulse-burst counter, a multiplexer in electronic communication with the subtractor module and the selection module, the multiplexer selecting from among at least two dead-time correction transforms, the transform corresponding to the selected pulse counter read-out rate, and a control-and-readout module that outputs a dead-time corrected pulse rate.

A counter readout circuit includes a plurality of counter registers and an output data computing unit. The plurality of counter registers, each includes a counter which counts per clock signal cycle. The output data computing unit includes a computing unit which adds, for output, the counter value of a counter register to the total clock count from a first timing to a second timing. The counter register is selected from the plurality of counter registers. The first timing is common to all of the plurality of counter registers. The second timing is a timing of selection of the selected counter register.

A counter readout circuit includes a plurality of counter registers and an output data computing unit. The plurality of counter registers, each includes a counter which counts per clock signal cycle. The output data computing unit includes a computing unit which adds, for output, the counter value of a counter register to the total clock count from a first timing to a second timing. The counter register is selected from the plurality of counter registers. The first timing is common to all of the plurality of counter registers. The second timing is a timing of selection of the selected counter register.

A system includes a pulse counter having a selectable pulse counter read-out rate, a pulse counter read-out (PCRO) storage register that stores a PCRO count, and a pulse-burst counter that has a pulse-burst counter read-out rate that is faster than all but the fastest selectable pulse counter read-out rate, a subtractor module in electronic communication with the pulse counter and the PCRO that subtracts the PCRO count from the pulse counter read-out count to output an uncorrected pulse count, a selection module in electronic communication with the pulse-burst counter that selects the pulse counter read-out rate in response to input from the pulse-burst counter, a multiplexer in electronic communication with the subtractor module and the selection module, the multiplexer selecting from among at least two dead-time correction transforms, the transform corresponding to the selected pulse counter read-out rate, and a control-and-readout module that outputs a dead-time corrected pulse rate.

A system includes a pulse counter having a selectable pulse counter read-out rate, a pulse counter read-out (PCRO) storage register that stores a PCRO count, and a pulse-burst counter that has a pulse-burst counter read-out rate that is faster than all but the fastest selectable pulse counter read-out rate, a subtractor module in electronic communication with the pulse counter and the PCRO that subtracts the PCRO count from the pulse counter read-out count to output an uncorrected pulse count, a selection module in electronic communication with the pulse-burst counter that selects the pulse counter read-out rate in response to input from the pulse-burst counter, a multiplexer in electronic communication with the subtractor module and the selection module, the multiplexer selecting from among at least two dead-time correction transforms, the transform corresponding to the selected pulse counter read-out rate, and a control-and-readout module that outputs a dead-time corrected pulse rate.