A liquid ejecting apparatus includes a drive element, and a drive circuit that outputs a drive signal that drives the drive element, wherein the drive circuit includes a modulation circuit that modulates a base drive signal to output a modulation signal, an amplifier circuit that amplifies the modulation signal to output an amplified modulation signal, a demodulation circuit that demodulates the amplified modulation signal to output the drive signal, and a substrate on which the modulation circuit, the amplifier circuit, and the demodulation circuit are provided, wherein the substrate includes a base material includes a metal and a first layer laminated on the base material, wherein the first layer includes a first propagation wire through which at least one of the amplified modulation signal and the drive signal propagates, and wherein the base material has a thickness greater than a thickness of the first layer.

A driving apparatus drives a load. An N-channel MOSFET is disposed downstream of the load on a current path of a current that flows via the load. A circuit resistor is connected between a direct current power source and the gate of the MOSFET. A first switch is connected between the gate and the source of the MOSFET. A microcomputer outputs a voltage relative to a potential at an output terminal of a second switch to a control terminal of the second switch. As a result, the second switch is turned ON or OFF. A switching circuit turns the first switch ON when the second switch is turned ON and turns the first switch OFF when the second switch is turned OFF.

A gate drive circuit according to an embodiment includes: a voltage detector that detects a voltage between a first terminal and a second terminal of a switching device; a delay circuit that outputs, with a delay for a predetermined time, a detected value of the voltage obtained from the voltage detector; and a first off-mode drive circuit and a second off-mode drive circuit that apply a control signal to a control terminal of the switching device for turning off the switching device, wherein the first off-mode drive circuit turns off the switching device faster than the second off-mode drive circuit, and stops its operation to turns off the switching device when the delayed voltage value output from the delay circuit exceeds a predetermined threshold value.

The present invention provides a power supply circuit with an adjustable channel switch impedance and an electronic device. The power supply circuit includes N main channel MOS transistors, a control module, an execution module and a detection module, wherein the execution module includes a first MOS transistor; the detection module includes a detection resistor and a second MOS transistor; a gate-source voltage of the main channel MOS transistors and a gate-source voltage of the first MOS transistor are configured to be consistent, and a source-drain voltage of the main channel MOS transistors and a source-drain voltage of the second MOS transistor are consistent; the control module is connected to the detection resistor and configured to: detect voltage drop information on voltage drop at two ends of the detection resistor, wherein the voltage drop information can represent a current of a load.

This disclosure describes systems, methods, and apparatuses for a PIN diode switch comprising series connected PIN diodes, the series connected PIN diodes comprising two or more PIN diodes connected in series, wherein each of the two or more PIN diodes comprises a first node and a second node; and an internal node positioned where a first node of a first PIN diode connects to a second node of a second, adjacent PIN diode; a RF bypass capacitor connected between a reference node and a first end of the series connected PIN diodes, and wherein a second end of the series connected PIN diodes is connected to the reference node; an RF circuit connected between the reference node and the internal node; and a PIN diode driver connected across the RF bypass capacitor.

A gate drive adapter circuit includes an input circuit, an output circuit, and a charge pump circuit. The input circuit is configured to receive pulses suitable for controlling a silicon power transistor. The output circuit is coupled to the input circuit. The output circuit is configured to translate the pulses to voltages suitable for controlling a silicon-carbide power transistor. The charge pump circuit is coupled to the input circuit and to the output circuit. The charge pump circuit is configured to generate a negative voltage. The output circuit is configured to apply the negative voltage to translate the pulses.

A driving device includes a voltage regulator, a voltage generator, and a first NMOSFET. The voltage regulator is coupled between a first high-voltage terminal and the output terminal of the driving device. The voltage regulator receives the first high voltage of the first high-voltage terminal. The voltage regulator steps down the first high voltage to generate a supply voltage. The voltage generator is coupled to a second high-voltage terminal and the output terminal of the driving device. The voltage generator provides a reference voltage for the output terminal of the driving device. The reference voltage is substantially lower than the supply voltage. The first NMOSFET is coupled between the output terminal of the driving device and a low-voltage terminal.

A driver circuit includes three sub-circuits. A first sub-circuit is configured to generate a drive current output by the driver circuit through an output node during first and second regions of operation and includes: a diode coupled to the output node and a first transistor, and a second transistor coupled to the first transistor and a current mirror. A second sub-circuit is configured to generate the drive current during the first and second and a third region of operation and includes: a third transistor coupled to the output node; and a fourth transistor. A third sub-circuit is configured to generate the drive current during the third region of operation and includes: a current source coupled to the current mirror and a buffer; and a fifth transistor coupled to the third transistor and the fourth transistor and configured to receive an output of the buffer.

A driver circuit may be configured to control a power switch. The driver circuit may comprise an output pin configured to deliver signals to a gate of the power switch to control an ON/OFF state of the power switch, and a comparator configured to compare a gate-to-source voltage of the power switch to a first threshold when the power switch is ON and to compare the gate-to-source voltage of the power switch to a second threshold when the power switch is OFF.

A gate driver circuit includes a pulse generator that receives an input signal and generates a pulse signal in response to a switch-on command included in the input signal. The pulse signal has a pulse with a pulse length that is dependent on a level of a pulse control signal. The circuit further includes a sampling circuit that samples an output voltage subsequent to the pulse and stores a respective sampled value, and a controller that receives the sampled value of the output voltage and a reference voltage and updates the level of the pulse control signal based on the sampled value and the reference voltage. A driver circuit generates the output voltage based on the pulse signal.