A semiconductor device including: NMOS transistors respectively having the drains, which are connectable to respective second terminals of boot capacitors of which respective first terminals are connectable to respective nodes at which high-side transistors and the low-side transistors are connected together, and the sources, which are electrically connectable to an application terminal for a supply voltage; and controllers driving respective gates of the plurality of NMOS transistors. When the high-side transistor for a first channel is kept off by the driver for the first channel, the high-side transistor for a second channel, which is different from the first channel, is kept on by the driver for the second channel. The controller for the first channel feeds a drive voltage based on the boot voltage for the second channel to the gate of the NMOS transistor for the first channel to keep on the NMOS transistor.

A circuit includes a high-side transistor pair and a low-side transistor pair having a common intermediate node. The high-side transistor pair includes a first transistor having a control node and a current flowpath therethrough configured to provide a current flow line between a supply voltage node and the intermediate node, and a second transistor having a current flowpath therethrough coupled to the control node of the first transistor. The low-side transistor pair includes a third transistor having a control node and a current flowpath therethrough configured to provide a current flow line between the intermediate node and the reference voltage node, and a fourth transistor having a current flowpath therethrough coupled to the control node of the third transistor. Testing circuitry is configured to be coupled to at least one of the second transistor and the fourth transistor to apply thereto a test-mode signal.

A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.

A level shift transistor of a first conductivity type configured to level shift a signal from a primary side circuit to a secondary side circuit between the primary side circuit having a primary side reference potential as reference and the secondary side circuit having a secondary side reference potential independent from the primary side reference potential as reference, a diode connected in a forward direction between a first main electrode of the level shift transistor and the secondary side circuit, a capacitor connected in parallel to the diode, and an inverter configured to invert the signal are provided. A control electrode of the level shift transistor is connected to a primary side power supply of the primary side circuit, and a second main electrode thereof is connected to an output of the inverter. The inverter operates between the primary side reference potential and the primary side power supply.

A semiconductor integrated circuit device includes a control unit configured to control a switching element or an output transistor of a power supply device, a monitor terminal for monitoring an output voltage of the power supply device, a test unit configured to output a test signal to the monitor terminal before activation of the power supply device, and a determination unit configured to determine whether or not the monitor terminal is open, on the basis of a voltage of the monitor terminal when the test unit outputs the test signal to the monitor terminal.

A circuit is disclosed. The circuit includes a current detecting FET, configured to generate a current signal indicative of the value of the current flowing therethrough, an operational transconductance amplifier (OTA) configured to output a current in response to the voltage of the current signal, and a resistor configured to receive the current and to generate a voltage in response to the received current, where the generated voltage is indicative of the value of the current flowing through the current detecting FET. The current detecting FET is configured to become nonconductive in response to the generated voltage indicating that the current flowing through the current detecting FET is greater than a threshold.

In accordance with an embodiment, a method of controlling a switch driver includes energizing a first inductor in a first direction with a first energy; transferring the first energy from the first inductor to a second inductor, wherein the second inductor is coupled between a second switch-driving terminal of the switch driver and a second internal node, and the second inductor is magnetically coupled to the first inductor; asserting a first turn-on signal at the second switch-driving terminal using the transferred first energy; energizing the first inductor in a second direction opposite the first direction with a second energy after asserting the first turn-on signal at the second switch-driving terminal; transferring the second energy from the first inductor to the second inductor; and asserting a first turn-off signal at the second switch-driving terminal using the transferred second energy.

A switch control circuit a multiplexer switch circuit and a control method for a multiplexer switch control circuit are provided. The switch control circuit comprises a first control switch, a first capacitor and a field-effect transistor switch. When the first control switch is switched off, a charging voltage released by the first capacitor can control the switching-on of the field-effect transistor switch. At this moment, since the first control switch is switched off, and a power source signal cannot reach a gate electrode of the field-effect transistor switch, power source noise cannot be coupled to a line where source and drain electrodes of the field-effect transistor switch are located. Thus, in a discharge stage of the first capacitor, a discharge voltage can serve as a control signal to control the switching-on of the field-effect transistor switch.

A current path to a gate is cut off by a normally-off first switch element until start-up of a gate drive voltage generator is sensed. Furthermore, a semiconductor switching element is maintained in an off state as a normally-on second switch element short-circuits the gate to a source. As start-up of the gate drive voltage generator is sensed, the second switch element is turned off and the first switch element is turned on. As the gate is thus driven by an output from a signal amplifier in accordance with a control signal, the semiconductor switching element is turned on and off in accordance with the control signal.

An apparatus includes a transistor coupled to a load through an output terminal of a load switch IC, a gate drive circuit connected to a gate of the transistor, wherein the gate drive circuit is configured such that in a short circuit event, a voltage on the gate of the transistor is gradually reduced, and wherein as a result of reducing the voltage on the gate of the transistor gradually, a negative voltage occurring at the output terminal of the load switch IC is minimized.