A bi-directional Gray code counter includes a first set of logic circuitry configured to receive an input having a first sequence of bits representing a first value. The first set of logic circuitry is further configured to convert the first sequence of bits to a second sequence of bits representing the first value. The bi-directional Gray code counter further includes a second set of logic circuitry and third second set of logic circuitry. The second set of logic circuitry is configured to compare the second sequence of bits to a bit index pattern. The third set of logic circuitry is configured to transition one bit in the first sequence of bits from a first state to a second state to form a third sequence of bits representing a second value. The one bit is transitioned in response to the second sequence of bits being compared to the bit index pattern.

A request to perform a read operation on a memory device is received. The memory device includes a first group of memory cells. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The read operation is performed by obtaining a first read signal for a first memory cell and a second read signal for a second memory cell of the first group of memory cells. A first rule logic is applied to the first read signal to generate a first updated signal and a second rule logic is applied to the second read signal to generate a second updated signal. Logic functions are applied to the first and second updated signals to generate an output signal indicating the first sequence of bits stored by the first group of memory cells.

A low power SRAM (static RAM) for an image sensor includes a voltage generation circuit for providing a positive supply voltage V.sub.P and a negative supply V.sub.N, wherein VDD>V.sub.p>V.sub.n>V.sub.gnd; a plurality of memory cells coupled to a respective plurality of column sense lines in a pixel array, the plurality of memory cells receiving differential inputs dp and dn; and a Gray counter coupled to switchably couple V.sub.P and V.sub.N to the differential inputs dp and dn of the plurality of memory cells. A method of operating an image sensor with a low power SRAM includes acquiring an image by the image sensor; generating V.sub.P and V.sub.N such that V.sub.DD>V.sub.P>V.sub.N>V.sub.gnd; receiving an output g of a column of pixels at a clock input of a memory cell; and switchably coupling V.sub.P and V.sub.N to the differential inputs dp and dn of a plurality of memory cells in the SRAM according to a codeword from a Gray counter.

A low power SRAM (static RAM) for an image sensor includes a voltage generation circuit for providing a positive supply voltage V.sub.P and a negative supply V.sub.N, wherein VDD>V.sub.p>V.sub.n>V.sub.gnd; a plurality of memory cells coupled to a respective plurality of column sense lines in a pixel array, the plurality of memory cells receiving differential inputs dp and dn; and a Gray counter coupled to switchably couple V.sub.P and V.sub.N to the differential inputs dp and dn of the plurality of memory cells. A method of operating an image sensor with a low power SRAM includes acquiring an image by the image sensor; generating V.sub.P and V.sub.N such that V.sub.DD>V.sub.P>V.sub.N>V.sub.gnd; receiving an output g of a column of pixels at a clock input of a memory cell; and switchably coupling V.sub.P and V.sub.N to the differential inputs dp and dn of a plurality of memory cells in the SRAM according to a codeword from a Gray counter.

An image sensor includes a pixel sensor that senses an incident light and outputs a sampling signal of an analog shape, a sampler that compares the sampling signal and a ramp signal and outputs a comparison signal being time-axis length information, and a gray counter that counts a length of the comparison signal in synchronization with a clock signal and outputs a digital value. The gray counter includes a first flip-flop that divides the clock signal by 2 and generates a first gray code signal, a second flip-flop that delays a first data signal being a four-divided signal of the clock signal and outputs a second gray code signal, and a third flip-flop that delays the second gray code signal being two-divided and outputs a third gray code signal.

A register circuit for which an initial value can be changed without using a flip-flop including both a set terminal and a reset terminal is provided. The register circuit includes an initial value wiring line, a write signal terminal, a clock signal terminal, a first flip-flop, an output control circuit, a second flip-flop, and a selector.

Systems, apparatuses, and methods for implementing a hybrid asynchronous gray counter with a non-gray zone detector are described. A circuit includes an asynchronous gray counter coupled to control logic. The control logic programs the asynchronous gray counter to operate in different modes to perform various functions associated with a high-performance phase-locked loop (PLL). In a first mode, the asynchronous gray counter serves as a frequency detector to count oscillator cycles within a reference clock cycle. In a second mode, the asynchronous gray counter serves as a coarse phase detector to detect a phase error between a feedback clock and a reference clock. In a third mode, the asynchronous gray counter serves as a multi-modulus divider to divide an oscillator clock down to create a feedback clock. Using a single asynchronous gray counter for three separate functions reduces power consumption and area utilization.

Apparatuses, systems and methods associated with bidirectional Gray code counter design are disclosed herein. In embodiments, a bidirectional Gray code counter may include a sequential logic element to store a Gray code value and logic circuitry. The logic circuitry may be to determine, based on a bidirectional indicator signal, whether to increment or decrement the Gray code value update, through performance of an increment or a decrement of the Gray code value based on the determination of whether to increment or decrement the Gray code value, the Gray code value to be a sequential Gray code value and replace the Gray code value stored in the sequential logic element with the updated Gray code value. Other embodiments may be described and/or claimed.

In described examples, a counter system includes a counter, a parity detector, a toggle flop, and a comparator. The counter iterates a count through a set of binary states in response to a clock signal, so that a binary value of a single bit of the count changes at each iteration. The parity detector detects the parity of the count. The toggle flop output is coupled to the toggle flop input. The toggle flop outputs a binary flop value. The binary flop value toggles between zero and one in response to the toggle flop input and the clock signal. The comparator compares the parity of the count and the toggle flop output, and outputs a first comparator value if the parity of the count and the toggle flop output are the same, and a second comparator value if the parity of the count and the toggle flop output are different.

In an embodiment, a method includes: providing a gray-coded time reference to a time-to-digital converter (TDC); receiving an event from an event signal; latching the gray-coded time reference into a memory upon reception of the event signal; and updating a time-of-flight (ToF) histogram based on the latched gray-coded time reference.