Disclosed is a frequency divider which includes a frequency dividing core circuit that includes a plurality of transistors and is configured to generate at least one division clock signal based on a clock signal and an inverted clock signal, a controller that is configured to generate a body bias control signal based on clock frequency information, and an adaptive body bias (ABB) generator that is configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.

Disclosed is a frequency divider which includes a frequency dividing core circuit that includes a plurality of transistors and is configured to generate at least one division clock signal based on a clock signal and an inverted clock signal, a controller that is configured to generate a body bias control signal based on clock frequency information, and an adaptive body bias (ABB) generator that is configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.

A dual-edge aware clock divider configured to generate an output clock based on the input clock and a ratio of an integer M over an integer N is disclosed herein. The frequency of the output clock is based on a frequency of the input clock multiplied by the ratio (M/N), wherein M may be set to a range up to N. The output clock includes M pulses within a sequence time window having a length of N periods of the input clock. The output clock includes one or more rising edges that are substantially time aligned with one or more rising edges and one or more falling edges of the input clock, respectively. The dual-edge aware clock divider is configured to generate the output clock based on inverted and non-inverted portions of the input clock. A hybrid clock divider including the dual-edge and single-edge aware techniques is provided.

A dual-edge aware clock divider configured to generate an output clock based on the input clock and a ratio of an integer M over an integer N is disclosed herein. The frequency of the output clock is based on a frequency of the input clock multiplied by the ratio (M/N), wherein M may be set to a range up to N. The output clock includes M pulses within a sequence time window having a length of N periods of the input clock. The output clock includes one or more rising edges that are substantially time aligned with one or more rising edges and one or more falling edges of the input clock, respectively. The dual-edge aware clock divider is configured to generate the output clock based on inverted and non-inverted portions of the input clock. A hybrid clock divider including the dual-edge and single-edge aware techniques is provided.

A shift register circuit including a flip-flop chain and a control circuit is provided. The flip-flop chain is configured to receive an input signal and output an output signal. The control circuit is coupled to the flip-flop chain. The control circuit is configured to receive the input signal and the output signal and output a control signal to activate the flip-flop chain according to edge transitions of the input signal and the output signal. In addition, a method for controlling a shift register circuit is also provided.

A shift register circuit including a flip-flop chain and a control circuit is provided. The flip-flop chain is configured to receive an input signal and output an output signal. The control circuit is coupled to the flip-flop chain. The control circuit is configured to receive the input signal and the output signal and output a control signal to activate the flip-flop chain according to edge transitions of the input signal and the output signal. In addition, a method for controlling a shift register circuit is also provided.

A counting device, including multiple counting circuit stages and a first logic operation circuit, is provided. The counting circuit stages are serially coupled in sequence. A first counting circuit stage performs a counting action according to a first clock signal and generates a first counting result. Second to Nth counting circuit stages perform counting actions according to a second clock signal, where N is a positive integer greater than 2. The first logic operation circuit provides the first counting result to be the second clock signal according to an indication signal.

A counting device, including multiple counting circuit stages and a first logic operation circuit, is provided. The counting circuit stages are serially coupled in sequence. A first counting circuit stage performs a counting action according to a first clock signal and generates a first counting result. Second to Nth counting circuit stages perform counting actions according to a second clock signal, where N is a positive integer greater than 2. The first logic operation circuit provides the first counting result to be the second clock signal according to an indication signal.

A detector slice circuit for a CT imaging system may include a plurality of sensors for detecting photons passing through an object and a first electronic component configured to determine an energy of photons detected by the plurality of sensors and generate photon count data, which may be a count of detected photons in one or more energy bins. The detector slice circuit may further include a second electronic component configured to receive the photon count data from the first electronic component and is clocked at a first clock rate; a local memory storage configured to receive the photon count data from the second electronic component at the first clock rate and to output the photon count data at a second clock rate.

An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.