A computational pixel imaging device that includes an array of pixel integrated circuits for event-based detection and imaging. Each pixel may include a digital counter that accumulates a digital number, which indicates whether a change is detected by the pixel. The counter may count in one direction for a portion of an exposure and count in an opposite direction for another portion of the exposure. The imaging device may be configured to collect and transmit key frames at a lower rate, and collect and transmit delta or event frames at a higher rate. The key frames may include a full image of a scene, captured by the pixel array. The delta frames may include sparse data, captured by pixels that have detected meaningful changes in received light intensity. High speed, low transmission bandwidth motion image video can be reconstructed using the key frames and the delta frames.

A stereo imaging system includes an optical assembly and a computational pixel imager (CPI) having a plurality of pixels. Each pixel includes a light sensor and counters that convert a photocurrent from the light sensor to a digital signal. The optical assembly, which directs light from a light field to the CPI, includes an optical field combiner and first and second primary lens assemblies, which are configured to receive first and second portions of the light from the light field, respectively, and to direct the first and second portions of the light to the optical field combiner. The optical field combiner includes a modulator configured to modulate the first and second portions of the light and to direct modulated first and second portions of the light onto the CPI. The counters are configured to perform digital signal processing on the digital signal.

A divider circuit includes a subtract-by-two circuit receiving MSBs of an input and producing a subtracted-by-two output, a subtract-by-one circuit receiving the MSBs and producing a subtracted-by-one output, a first multiplexer passing the subtracted-by-two or the subtracted-by-one output based on a first control signal, a second multiplexer passing output of the first multiplexer or the MSBs based on a second control signal to produce an asynchronous divisor. An asynchronous one-shot N+2 divider divides an input clock by the asynchronous divisor to produce a first divided signal. An output flip-flop receives the first divided signal and is clocked by an inverse of the input clock to produce a second divided signal. A third multiplexer passes the first divided signal or the second divided signal in response to a select load signal to produce a multiplexer output. A divider divides the multiplexer output by a set divisor to produce an output clock.

Disclosed is an open loop fractional frequency divider including an integer divider, a control circuit, and a phase interpolator. The integer divider processes an input clock according to the setting of a target frequency to generate a first frequency-divided clock and a second frequency-divided clock. The control circuit generates a coarse-tune control signal and a fine-tune control signal according to the setting. The phase interpolator generates an output clock according to the first frequency-divided clock, the second frequency-divided clock, and the two control signals. The two control signals are used for determining a first current, and their reversed signals are used for determining a second current. The phase interpolator controls a contribution of the first (second) frequency-divided clock to the generation of the output clock according to the first (second) frequency-divided clock, the reversed signal of the first (second) frequency-divided clock, and the first (second) current.

A computational pixel imaging device that includes an array of pixel integrated circuits for event-based detection and imaging. Each pixel may include a digital counter that accumulates a digital number, which indicates whether a change is detected by the pixel. The counter may count in one direction for a portion of an exposure and count in an opposite direction for another portion of the exposure. The imaging device may be configured to collect and transmit key frames at a lower rate, and collect and transmit delta or event frames at a higher rate. The key frames may include a full image of a scene, captured by the pixel array. The delta frames may include sparse data, captured by pixels that have detected meaningful changes in received light intensity. High speed, low transmission bandwidth motion image video can be reconstructed using the key frames and the delta frames.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

Disclosed is an open loop fractional frequency divider including an integer divider, a control circuit, and a phase interpolator. The integer divider processes an input clock according to the setting of a target frequency to generate a first frequency-divided clock and a second frequency-divided clock. The control circuit generates a coarse-tune control signal and a fine-tune control signal according to the setting. The phase interpolator generates an output clock according to the first frequency-divided clock, the second frequency-divided clock, and the two control signals. The two control signals are used for determining a first current, and their reversed signals are used for determining a second current. The phase interpolator controls a contribution of the first (second) frequency-divided clock to the generation of the output clock according to the first (second) frequency-divided clock, the reversed signal of the first (second) frequency-divided clock, and the first (second) current.

A stereo imaging system includes an optical assembly and a computational pixel imager (CPI) having a plurality of pixels. Each pixel includes a light sensor and counters that convert a photocurrent from the light sensor to a digital signal. The optical assembly, which directs light from a light field to the CPI, includes an optical field combiner and first and second primary lens assemblies, which are configured to receive first and second portions of the light from the light field, respectively, and to direct the first and second portions of the light to the optical field combiner. The optical field combiner includes a modulator configured to modulate the first and second portions of the light and to direct modulated first and second portions of the light onto the CPI. The counters are configured to perform digital signal processing on the digital signal.

A computational pixel imaging device can include multiple digitizing counters per pixel that can be used to execute simultaneous signal-processing threads on acquired image data. The imaging device can also include infinite dynamic range sensing and perform signal down- sampling.

A stereo imaging system includes an optical assembly and a computational pixel imager (CPI) having a plurality of pixels. Each pixel includes a light sensor and counters that convert a photocurrent from the light sensor to a digital signal. The optical assembly, which directs light from a light field to the CPI, includes an optical field combiner and first and second primary lens assemblies, which are configured to receive first and second portions of the light from the light field, respectively, and to direct the first and second portions of the light to the optical field combiner. The optical field combiner includes a modulator configured to modulate the first and second portions of the light and to direct modulated first and second portions of the light onto the CPI. The counters are configured to perform digital signal processing on the digital signal.