In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.

A method can include, in response to a power supply voltage transition, setting a temperature window to a first temperature range by operation of a temperature circuit formed on a semiconductor device. In response to a temperature of the semiconductor device being determined to be outside of the first temperature range, changing the temperature range of the temperature window until the temperature of the semiconductor device is determined to be within the temperature window.

A method can include, in response to a power supply voltage transition, setting a temperature window to a first temperature range by operation of a temperature circuit formed on a semiconductor device. In response to a temperature of the semiconductor device being determined to be outside of the first temperature range, changing the temperature range of the temperature window until the temperature of the semiconductor device is determined to be within the temperature window.

This invention, is concerning a signal voltage device, in which transformers 22a, 22b and a reception circuit 24 are formed on the same chip, and accordingly, no ESD protective element connected to a transformer connection terminal of the reception circuit 24 is required, and negative pulses generated in reception-side inductors 11 can be used in signal transmission. Signal transmission using both positive pulses and negative pulses is made possible as a result, and a stable signal transmission operation can be carried out even in a case where delay time varies in a signal detection circuit. Further, a reception circuit of low power consumption can be configured by using a single-ended Schmitt trigger circuit 14 in the signal detection circuit.

This invention, is concerning a signal voltage device, in which transformers 22a, 22b and a reception circuit 24 are formed on the same chip, and accordingly, no ESD protective element connected to a transformer connection terminal of the reception circuit 24 is required, and negative pulses generated in reception-side inductors 11 can be used in signal transmission. Signal transmission using both positive pulses and negative pulses is made possible as a result, and a stable signal transmission operation can be carried out even in a case where delay time varies in a signal detection circuit. Further, a reception circuit of low power consumption can be configured by using a single-ended Schmitt trigger circuit 14 in the signal detection circuit.

In an embodiment, an integrated circuit includes a clock tree circuit and logic circuitry that is clocked by the clocks received from the clock tree circuit. The logic circuit is powered by a first power supply voltage. The integrated circuit includes a voltage regulator that receives the first power supply voltage and generates a second power supply voltage having a magnitude that is lower than the magnitude of the first power supply voltage by a predetermined amount. The second power supply voltage may track the first power supply voltage over dynamic changes during use, either intentional changes to operating state or noise-induced changes. The second power supply voltage may be used to power at least a portion of the clock tree.

An integrated circuit includes first and second bus terminals, a pass-gate transistor, first and rising time accelerator (RTA) control circuits, and first and second falling time accelerator (FTA) control circuits. The pass-gate transistor couples between the first and second bus terminals. The first RTA control circuit couples to the first bus terminal, detects a rising edge on the first bus terminal, and accelerates the rising edge on the first bus terminal. The first FTA control circuit couples to the first bus terminal, detects a falling edge on the first bus terminal having a slope below a threshold, and accelerates the falling edge on the first bus terminal. The second RTA and FTA control circuits function similar to the first RTA and FTA control circuits but with respect to the second bus terminal.

An integrated circuit includes first and second bus terminals, a pass-gate transistor, first and rising time accelerator (RTA) control circuits, and first and second falling time accelerator (FTA) control circuits. The pass-gate transistor couples between the first and second bus terminals. The first RTA control circuit couples to the first bus terminal, detects a rising edge on the first bus terminal, and accelerates the rising edge on the first bus terminal. The first FTA control circuit couples to the first bus terminal, detects a falling edge on the first bus terminal having a slope below a threshold, and accelerates the falling edge on the first bus terminal. The second RTA and FTA control circuits function similar to the first RTA and FTA control circuits but with respect to the second bus terminal.

A dynamic D flip-flop with an inverted output involves an input end (101) used for receiving input data; an output end (102) used for providing output data to respond to the input data; a clock signal end (103) used for receiving a clock signal; a first latch (104) used for latching the input data from the input end (101) and performing inverting transmission on the input data under the control of the clock signal; a second latch (105) used for latching data from the first latch (104) and performing inverting transmission on the data latched by the first latch (104) under the control of the clock signal; and an inverter (106) used for performing inverting output on the data received from the second latch (105), the first latch (104), the second latch (105), and the inverter (106) being sequentially connected in series between the input end and the output end.

A dynamic D flip-flop with an inverted output involves an input end (101) used for receiving input data; an output end (102) used for providing output data to respond to the input data; a clock signal end (103) used for receiving a clock signal; a first latch (104) used for latching the input data from the input end (101) and performing inverting transmission on the input data under the control of the clock signal; a second latch (105) used for latching data from the first latch (104) and performing inverting transmission on the data latched by the first latch (104) under the control of the clock signal; and an inverter (106) used for performing inverting output on the data received from the second latch (105), the first latch (104), the second latch (105), and the inverter (106) being sequentially connected in series between the input end and the output end.