A retention flip-flop includes a master latch outputting a first signal which is generated based on a signal inputted through an input terminal based on first control signals; a slave latch outputting a second signal generated based on the first signal based on the first control signals and second control signals; and a control logic that generates the first control signals based on a clock signal and provides the first control signals to the master latch and the slave latch, and generates the second control signals based on a power down signal and provides the second control signals to the slave latch. The slave latch comprises a retention latch which transmits the first signal to an output terminal as the second signal by operating as an open loop based on the second control signals or maintains the second signal by forming a closed loop based on the second control signals.

A retention flip-flop includes a master latch outputting a first signal which is generated based on a signal inputted through an input terminal based on first control signals; a slave latch outputting a second signal generated based on the first signal based on the first control signals and second control signals; and a control logic that generates the first control signals based on a clock signal and provides the first control signals to the master latch and the slave latch, and generates the second control signals based on a power down signal and provides the second control signals to the slave latch. The slave latch comprises a retention latch which transmits the first signal to an output terminal as the second signal by operating as an open loop based on the second control signals or maintains the second signal by forming a closed loop based on the second control signals.

Apparatus and methods for clock duty cycle correction and deskew are provided. In certain embodiments, a clock distribution circuit includes a clock driver that provides a differential clock signal to a clock slicer over a pair of transmission lines. The clock distribution circuit further includes a resistor-inductor-capacitor (RLC) tuning circuit for providing termination between the pair of transmission lines and a differential input to the clock slicer. The RLC tuning circuit includes a pair of resistor digital-to-analog converters (resistor DACs or RDACs) coupled to the pair of transmission lines and a pair of controllable inductor-capacitor (LC) circuits coupled to the pair of transmission lines.

Apparatus and methods for clock duty cycle correction and deskew are provided. In certain embodiments, a clock distribution circuit includes a clock driver that provides a differential clock signal to a clock slicer over a pair of transmission lines. The clock distribution circuit further includes a resistor-inductor-capacitor (RLC) tuning circuit for providing termination between the pair of transmission lines and a differential input to the clock slicer. The RLC tuning circuit includes a pair of resistor digital-to-analog converters (resistor DACs or RDACs) coupled to the pair of transmission lines and a pair of controllable inductor-capacitor (LC) circuits coupled to the pair of transmission lines.

Provided is a switching apparatus, including: a first semiconductor switching device of IGBT, and a second semiconductor switching device of a different type from IGBT, which are electrically connected in parallel; and a control unit configured to turn on the second semiconductor switching device before the first semiconductor switching device, wherein a maximum rated current of the second semiconductor switching device is greater than a maximum rated current of the first semiconductor switching device.

A high voltage pulse generator is disclosed. The high voltage pulse generator comprises a pulse generating transformer having a primary coil with a first side and a second side, and a secondary coil with a first side and a second side. A direct current (DC) voltage source connection is at the first side of the primary coil. A first high frequency power driver transistor is coupled between the second side of the primary coil and a ground connection. The first high frequency power driver transistor is configured to operate in an on-mode for a selected time period to charge the primary coil for the selected time period based on a switching frequency of the first high frequency power driver transistor, and switch the first high frequency power driver transistor to an off-mode at the switching frequency to release the charge from the primary coil to the secondary coil. A diode is coupled between the first side of the secondary coil and a pulsed voltage output that is configured to be connected to a high voltage device. The diode configured to direct a flow of charge from the secondary coil to charge a capacitance of the high voltage device to a rising pulse leading edge of a voltage pulse.

A high voltage pulse generator is disclosed. The high voltage pulse generator comprises a pulse generating transformer having a primary coil with a first side and a second side, and a secondary coil with a first side and a second side. A direct current (DC) voltage source connection is at the first side of the primary coil. A first high frequency power driver transistor is coupled between the second side of the primary coil and a ground connection. The first high frequency power driver transistor is configured to operate in an on-mode for a selected time period to charge the primary coil for the selected time period based on a switching frequency of the first high frequency power driver transistor, and switch the first high frequency power driver transistor to an off-mode at the switching frequency to release the charge from the primary coil to the secondary coil. A diode is coupled between the first side of the secondary coil and a pulsed voltage output that is configured to be connected to a high voltage device. The diode configured to direct a flow of charge from the secondary coil to charge a capacitance of the high voltage device to a rising pulse leading edge of a voltage pulse.

A clocked storage element comprises a first latch having an input data node, a clock input node and a first latch output data node, and a second latch having an input connected to the first latch output data node, a clock input node and a second latch output data node. The first and second latches can have a clocked pull-up current path consisting of two p-channel transistors between their respective output data nodes and the VDD supply line, and a clocked pull-down current path consisting of two n-channel transistors between their respective output data nodes and the VSS supply line.

A clocked storage element comprises a first latch having an input data node, a clock input node and a first latch output data node, and a second latch having an input connected to the first latch output data node, a clock input node and a second latch output data node. The first and second latches can have a clocked pull-up current path consisting of two p-channel transistors between their respective output data nodes and the VDD supply line, and a clocked pull-down current path consisting of two n-channel transistors between their respective output data nodes and the VSS supply line.

In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.