A method of stabilizing data of digital signals is provided. The method includes steps of: (a) determining whether or not next input data is larger than previous output data, if yes, adding a base value to a trend value and then performing step(c), if no, performing step(b); (b) determining whether or not the next input data is smaller than the previous output data, if yes, subtracting the base value from the trend value and performing step(c), if no, performing step(c); (c) determining whether or not the trend value is larger than a positive threshold, if yes, subtracting a trend correction coefficient from the previous output data, if no, performing step(d); and (d) determining whether or not the trend value is smaller than a negative threshold, if yes, adding the trend correction coefficient to the previous output data; if no, outputting the previous output data.

A method of stabilizing data of digital signals is provided. The method includes steps of: (a) determining whether or not next input data is larger than previous output data, if yes, adding a base value to a trend value and then performing step(c), if no, performing step(b); (b) determining whether or not the next input data is smaller than the previous output data, if yes, subtracting the base value from the trend value and performing step(c), if no, performing step(c); (c) determining whether or not the trend value is larger than a positive threshold, if yes, subtracting a trend correction coefficient from the previous output data, if no, performing step(d); and (d) determining whether or not the trend value is smaller than a negative threshold, if yes, adding the trend correction coefficient to the previous output data; if no, outputting the previous output data.

A system includes a level shifter coupled to a voltage source, a first transistor, and a second transistor. The system also includes a first current source coupled to the first transistor and the second transistor and configured to bias the first transistor and the second transistor. The system includes a slew detector coupled to the voltage source and to the first current source, where the slew detector is configured to detect a change in voltage of the voltage source, and further configured to provide current to the first current source responsive to detecting the change. The system also includes a second current source coupled in parallel to the first current source, where the second current source is configured to provide current to the first current source responsive to a control signal.

A system includes a level shifter coupled to a voltage source, a first transistor, and a second transistor. The system also includes a first current source coupled to the first transistor and the second transistor and configured to bias the first transistor and the second transistor. The system includes a slew detector coupled to the voltage source and to the first current source, where the slew detector is configured to detect a change in voltage of the voltage source, and further configured to provide current to the first current source responsive to detecting the change. The system also includes a second current source coupled in parallel to the first current source, where the second current source is configured to provide current to the first current source responsive to a control signal.

The present invention provides a Schmitt trigger circuit in which chattering does not occur in the output of the Schmitt trigger circuit even when it is connected to a communication bus without impedance matching and reflected noise is superimposed on the input signal. The Schmitt trigger circuit includes: a first signal detection circuit; a second signal detection circuit; a latch circuit; a selection signal generation circuit; a first input port; and a first output port. The first signal detection circuit is connected to the first input port, the latch circuit and the selection signal generation circuit. The second signal detection circuit is connected to the first input port, the latch circuit and the selection signal generation circuit. The latch circuit is connected to the selection signal generation circuit and the output port. The selection signal generation circuit includes a delay circuit.

The present invention provides a Schmitt trigger circuit in which chattering does not occur in the output of the Schmitt trigger circuit even when it is connected to a communication bus without impedance matching and reflected noise is superimposed on the input signal. The Schmitt trigger circuit includes: a first signal detection circuit; a second signal detection circuit; a latch circuit; a selection signal generation circuit; a first input port; and a first output port. The first signal detection circuit is connected to the first input port, the latch circuit and the selection signal generation circuit. The second signal detection circuit is connected to the first input port, the latch circuit and the selection signal generation circuit. The latch circuit is connected to the selection signal generation circuit and the output port. The selection signal generation circuit includes a delay circuit.

A flip flop includes a precharge circuit configured to charge a first node by bridging a power voltage node and the first node, the charging of the first node by the precharge circuit according to a voltage level of a clock signal, the charging of the first node by the precharge circuit based on at least two PMOS transistors arranged in series, a discharge circuit configured to discharge the first node by bridging the first node and a ground node, the discharging of the first node according to an input signal and the clock signal, and a second node configured to be charged or discharged, the charging and the discharging of the second node according to a voltage level of the first node.

A flip flop includes a precharge circuit configured to charge a first node by bridging a power voltage node and the first node, the charging of the first node by the precharge circuit according to a voltage level of a clock signal, the charging of the first node by the precharge circuit based on at least two PMOS transistors arranged in series, a discharge circuit configured to discharge the first node by bridging the first node and a ground node, the discharging of the first node according to an input signal and the clock signal, and a second node configured to be charged or discharged, the charging and the discharging of the second node according to a voltage level of the first node.

The disclosure is directed to a power module apparatus that includes a base plate, a power substrate positioned relative to the base plate, at least two power contacts, a gate-source board mounted relative to the power substrate, gate drive connectors electrically connected to the gate-source board, a housing secured to the power substrate, and a clamping circuit electrically connected to the at least one power device. The clamping circuit being configured to clamp an input to a gate of the at least one power device. The clamping circuit being arranged with at least one of the following: the base plate, the power substrate, one of the at least two power contacts, the at least one power device, the gate-source board, the gate drive connectors, and the housing. The disclosure is further directed to a process of configuring a power module apparatus.

The disclosure is directed to a power module apparatus that includes a base plate, a power substrate positioned relative to the base plate, at least two power contacts, a gate-source board mounted relative to the power substrate, gate drive connectors electrically connected to the gate-source board, a housing secured to the power substrate, and a clamping circuit electrically connected to the at least one power device. The clamping circuit being configured to clamp an input to a gate of the at least one power device. The clamping circuit being arranged with at least one of the following: the base plate, the power substrate, one of the at least two power contacts, the at least one power device, the gate-source board, the gate drive connectors, and the housing. The disclosure is further directed to a process of configuring a power module apparatus.