An event detection controller for a circuit system controlled by a pulse wave modulation signal, can perform a specific event handling when a specific event is detected, wherein the specific event handling includes stopping a pulse wave modulation device, starting up the stopped pulse wave modulation device, controlling the pulse wave modulation device to change the pulse wave modulation signal, outputting a wake-up signal to wake up the circuit system, controlling the pulse detector to change its detection configuration, changing a cumulative occurrences number of the specific pattern of an event discrimination module, outputting a control signal or a first data signal to a peripheral device through a bus connected to an event response module and/or requesting the peripheral device to send a second data signal through the bus.

A switch circuit of an embodiment includes a high frequency switch, a first charge pump circuit, a boost signal generation circuit, and a second charge pump circuit. The high frequency switch switches transmission and reception of a high frequency signal. The first charge pump circuit generates a first voltage and a second voltage biased to the high frequency switch. When an edge of an input signal is detected, the boost signal generation circuit generates a first boost signal for temporarily increasing drive capacity of the first charge pump circuit. When the first boost signal is input, the second charge pump circuit operates to temporarily increase the drive capacity of the first charge pump circuit.

A switch circuit of an embodiment includes a high frequency switch, a first charge pump circuit, a boost signal generation circuit, and a second charge pump circuit. The high frequency switch switches transmission and reception of a high frequency signal. The first charge pump circuit generates a first voltage and a second voltage biased to the high frequency switch. When an edge of an input signal is detected, the boost signal generation circuit generates a first boost signal for temporarily increasing drive capacity of the first charge pump circuit. When the first boost signal is input, the second charge pump circuit operates to temporarily increase the drive capacity of the first charge pump circuit.

A soft-start circuit which can be applied to a motor controller is provided. The soft-start circuit comprises a controller, a counting unit, a digital-to-analog converter, a current detecting unit, and a comparator. The soft-start circuit uses a plurality of current limit values so as to achieve a maximum output power and prevent damage to a motor coil.

A clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.

A clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.

The present disclosure discloses a driving circuit and a related chip and electronic device. The driving circuit is configured to drive a load and includes: a control unit, configured to generate a first control signal and a second control signal; a first output terminal, coupled to the capacitive touch screen; a mutual capacitive driving circuit, including: a first pull-up unit, configured to selectively pull up the first output terminal coupled to a high voltage level according to the first control signal; a first pull-down unit, configured to selectively couple the first output terminal to a low voltage level according to the second control signal; a first low-pass filter circuit, coupled between the control unit and the first pull-up unit; and a second low-pass filter circuit, coupled between the control unit and the first pull-down unit.

The present disclosure discloses a driving circuit and a related chip and electronic device. The driving circuit is configured to drive a load and includes: a control unit, configured to generate a first control signal and a second control signal; a first output terminal, coupled to the capacitive touch screen; a mutual capacitive driving circuit, including: a first pull-up unit, configured to selectively pull up the first output terminal coupled to a high voltage level according to the first control signal; a first pull-down unit, configured to selectively couple the first output terminal to a low voltage level according to the second control signal; a first low-pass filter circuit, coupled between the control unit and the first pull-up unit; and a second low-pass filter circuit, coupled between the control unit and the first pull-down unit.

The present invention provides an offset calibration circuit used in a signal processing circuit, wherein the offset calibration circuit includes a supply voltage detection circuit and a calibration circuit. The supply voltage detection circuit is configured to detect a level of a supply voltage to generate a detection result, wherein the supply voltage is provided to an output stage in the signal processing circuit. The calibration circuit is configured to calculate a digital compensation value according to the detection result, wherein the digital compensation value is used for a digital processing circuit in the signal processing circuit to perform a DC offset calibration.

The present invention provides an offset calibration circuit used in a signal processing circuit, wherein the offset calibration circuit includes a supply voltage detection circuit and a calibration circuit. The supply voltage detection circuit is configured to detect a level of a supply voltage to generate a detection result, wherein the supply voltage is provided to an output stage in the signal processing circuit. The calibration circuit is configured to calculate a digital compensation value according to the detection result, wherein the digital compensation value is used for a digital processing circuit in the signal processing circuit to perform a DC offset calibration.