Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more

A circuit apparatus includes an oscillation circuit that generates an oscillation signal, a first buffer circuit that outputs a first clock signal based on the oscillation signal, a second buffer circuit that outputs a second clock signal based on the first clock signal, a first terminal electrically couplable to a first node via which the first buffer circuit outputs the first clock signal, and a second terminal electrically coupled to a second node via which the second buffer circuit outputs the second clock signal, and the rise period of the first clock signal is shorter than the rise period of the second clock signal.

A clock generating device, a controller and a storage device. The clock generating device comprises: a clock generator counter outputting a clock trigger signal according to a clock period of each reference number of a reference clock; a compensation counter module outputting a compensation signal, the compensation counter module comprises: a first compensation counter outputting a first compensation clock according to a clock period of each first compensation number of the reference clock, the first compensation number is greater than the reference number, the compensation signal includes the first compensation clock; and a clock generator, when the compensation signal is in a first state, the clock generator generates a target clock signal according to the clock trigger signal; when the compensation signal is in a second state, the clock generator cancels a corresponding pulse in the clock trigger signal according to the compensation signal to generate the target clock signal.

The present disclosure provides an adaptive adjustment circuit in a computer chip having a voltage-controlled oscillator (VCO) and a processor. The adaptive adjustment circuit comprises a frequency difference acquisition module to generate a frequency difference signal based on a first difference between an oscillation frequency of the VCO and a target frequency. The adaptive adjustment circuit also includes a power module to supply a working voltage to the VCO and the processor, adjust the working voltage based on the frequency difference signal, and supply the adjusted working voltage to the VCO and the processor.

Voltage monitoring circuit having an analog reset signal generator to generate a reset signal and coupled to a voltage to be monitored; first register to store a first state bit and coupled to the voltage to be monitored; second register connected in parallel to the first register, redundant to the first register, to store a second state bit, and coupled to the voltage to be monitored; logic coupled to the first and second registers and to determine a state control signal from the first and second state bits, and a second reset signal; and OR logic to receive the following signals on the input side and process them with one another according to an OR operation: a first reset signal generated by the analog reset signal generator and the second reset signal, so that a reset control signal is generated and fed to reset inputs of the registers.

Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.

A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

Voltage monitoring circuit having an analog reset signal generator to generate a reset signal and coupled to a voltage to be monitored; first register to store a first state bit and coupled to the voltage to be monitored; second register connected in parallel to the first register, redundant to the first register, to store a second state bit, and coupled to the voltage to be monitored; logic coupled to the first and second registers and to determine a state control signal from the first and second state bits, and a second reset signal; and OR logic to receive the following signals on the input side and process them with one another according to an OR operation: a first reset signal generated by the analog reset signal generator and the second reset signal, so that a reset control signal is generated and fed to reset inputs of the registers.

A circuit apparatus includes an oscillation circuit that generates an oscillation signal, a first buffer circuit that outputs a first clock signal based on the oscillation signal, a second buffer circuit that outputs a second clock signal based on the first clock signal, a first terminal electrically couplable to a first node via which the first buffer circuit outputs the first clock signal, and a second terminal electrically coupled to a second node via which the second buffer circuit outputs the second clock signal, and the rise period of the first clock signal is shorter than the rise period of the second clock signal.

The present disclosure provides an adaptive adjustment circuit in a computer chip having a voltage-controlled oscillator (VCO) and a processor. The adaptive adjustment circuit comprises a frequency difference acquisition module to generate a frequency difference signal based on a first difference between an oscillation frequency of the VCO and a target frequency. The adaptive adjustment circuit also includes a power module to supply a working voltage to the VCO and the processor, adjust the working voltage based on the frequency difference signal, and supply the adjusted working voltage to the VCO and the processor.