An integrated circuit device includes a digitally controlled oscillator (DCO), two charge-sharing capacitors, two charge-sharing switches, two pre-charge switches, and two DACs. The DCO has a first inverter and a second inverter. A first charge-sharing capacitor has a first terminal coupled to an input terminal of the first inverter through a first charge-sharing switch. A first DAC has an output terminal coupled to the first terminal of the first charge-sharing capacitor through a first pre-charge switch. A second charge-sharing capacitor has a first terminal coupled to an input terminal or an output terminal of the second inverter through a second charge-sharing switch. A second DAC has an output terminal coupled to the first terminal of the second charge-sharing capacitor through a second pre-charge switch.

An apparatus comprises a first circuit, a second circuit, a first transistor, a second transistor, a third transistor, a first programmable resistance, and a second programmable resistance. The first circuit may be configured to generate a reference signal and a bias signal in response to a supply voltage and a first input signal. The first circuit generally provides supply noise rejection to variations in the supply voltage. The second circuit may be connected to the first circuit and a ring oscillator. The first transistor may be connected to the first circuit and configured to set a first reference current of the first circuit based on the first input signal and the first programmable resistance. The second transistor may be connected in parallel with the first transistor. The second transistor is generally diode-connected. The third transistor may be connected to the first circuit and configured to set a second reference current of the first circuit based on the first input signal and the second programmable resistance. The first circuit generally forms a current mirror with the second circuit. The second circuit may be configured to provide a programmable current ratio for the current mirror based on a value of a second input signal.

One example includes an Ising machine system. The system includes a plurality of ring oscillators that are each configured to propagate an oscillation signal. Each of the ring oscillators can be cross-coupled with at least one other of the ring oscillators via a respective one of the oscillation signals to provide a respective phase coupling between the respective cross-coupled ring oscillators. The system also includes an Ising machine controller configured to generate control signals corresponding to parameters of an Ising problem and including a plurality of delay selection signals. The Ising machine controller can provide at least one of the delay selection signals to each of the ring oscillators. The delay selection signal can be configured to set a variable propagation delay of the ring oscillator to control the relative phase coupling of each of the ring oscillators to each of the at least one other of the ring oscillators.

A semiconductor integrated circuit includes a first oscillator configured to generate a first signal with a first frequency based on a control signal and output the first signal to a path. The semiconductor integrated circuit includes a control signal generation circuit operatively coupled to the first oscillator via the path, and configured to receive the first signal from the first oscillator via the path and generate the control signal. The semiconductor integrated circuit includes a second oscillator configured to generate a second signal with a second frequency based on the control signal and output the second signal to an output terminal outside the path.

A crystal-free wireless device includes a frequency calibration module and a local radio frequency (RF) oscillator having a first frequency and configured to communicate with the frequency calibration module. The crystal-free wireless device also includes a relaxation ring oscillator configured to communicate with the frequency calibration module. The relaxation ring oscillator is further configured to receive a calibration signal or periodic radio frequency packets from a wireless network and provide a reference signal to the frequency calibration module. The relaxation ring oscillator is a crystal-free oscillator. The frequency calibration module is configured to generate a calibration signal that is fed back through a Frequency Locked Loop (FLL) to the local RF oscillator to calibrate the local RF oscillator. The calibrated local RF oscillator is configured to generate a clock signal.

This disclosure provides a voltage controlled oscillator and a control method thereof, a P2P interface circuit, an electronic device, and relates to the field of voltage controlled oscillation technology. The voltage controlled oscillator includes N stages of delay units, and the delay unit of each stage includes: a first inverter, a second inverter, a third inverter, and a fourth inverter; both the second inverter and the third inverter are electrically connected to a frequency control terminal, and whether to activate the second inverter and the third inverter is controlled by the frequency control terminal.

An electronic device comprises a regulator, and an oscillator and a resistor coupled to the regulator. The electronic device further comprises a feedback controller that includes a differential amplifier coupled between the oscillator, the resistor, and the regulator. The feedback controller is configured to apply a control voltage to the regulator in response to a resistor voltage upon the resistor and an oscillator voltage upon the oscillator. The feedback controller can be coupled to control a substantially equal voltage upon the resistor and the oscillator.

Techniques and mechanisms for determining calibration information based on tuning of a ring oscillator circuit formed with two integrated circuit (IC) dies. In an embodiment, an oscillator circuit comprises an in-series arrangement of delay circuits including a first one or more delay circuits of a first die, and a second one or more delay circuits of a second die. Respective circuitry of the first die and the second die performs tuning to match an oscillation frequency of the oscillator circuit with a reference frequency. An operational setting of the tuned oscillator circuit is provided to calibrate transmitter circuitry of the first die and the second die. In another embodiment, tuning of the oscillator circuit is further based on tuning of a local oscillator circuit of one of the first die or the second die.

The present technology includes a replica circuit and an oscillator including the same. The replica circuit includes a first terminal to which a replica voltage having a positive voltage is supplied, a second terminal to which a ground voltage is supplied, a replica main circuit connected between the first terminal and the second terminal and configured to form a first current path in response to the replica voltage, and a replica sub circuit connected in parallel with the replica main circuit between the first terminal and the second terminal and configured to form a second current path in response to the replica voltage. A current flowing through the second current path having a replica sub current amount is less than a current flowing through the first current path having a replica main current amount.

A system for generating a sub-harmonically injection locked phase interpolated output signal. The system comprises ring oscillator (RO) circuitry to generate an output oscillator signal in response to a periodic input signal. The RO circuitry includes a plurality of differential delay RO stages interconnected in cascade within a closed loop, where each RO stage is configured to establish a corresponding delayed version of the output oscillator signal successively shifted in phase by a predetermined phase difference based on a predetermined interpolation mapping scheme. The system further comprises signal injection circuitry coupled to the RO circuitry to apply a first signal having a first input phase and a second signal having a second input phase to the plurality of differential delay RO stages based on the predetermined interpolation mapping scheme to lock a frequency of the output oscillator signal at one half the frequency of the periodic input signal.