H03K3/033

Sterile field interactive control displays

An interactive control unit is disclosed. The interactive control unit includes an interactive touchscreen display, an interface configured to couple the control unit to a surgical hub, a processor, and a memory coupled to the processor. The memory stores instructions executable by the processor to receive input commands from the interactive touchscreen display located inside a sterile field and transmit the input commands to the surgical hub to control devices coupled to the surgical hub located outside the sterile field.

DRIVING CIRCUIT
20170237422 · 2017-08-17 ·

Voltage surge is prevented when the output from a driver of a driving circuit performs a hard shutdown. In this manner, the elements in the driving circuit are prevented from being damaged by the voltage surge. A driving circuit includes a level shift circuit configured to convert an input signal from a preceding-stage circuit into an output signal having a higher voltage than the input signal, and a controller configured to determine whether a switch element is to perform a soft shutdown based on a state signal indicating a state of the preceding-stage circuit. Here, the driving circuit is configured to drive the switch element.

PULSE-GENERATOR

The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The first latch input may be coupled to a fixed logic value. The one of the set input or the reset input may be coupled to a clock signal or an inverted clock signal, respectively. The apparatus may include an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output. The clock signal may be coupled to the first AND gate input. The first latch output may be coupled to the second AND gate input. The AND gate output may be configured to output a pulsed clock. The pulsed clock may be coupled to the first pulse clock input.

Frequency Converter
20210399632 · 2021-12-23 ·

A frequency converter includes: at least one bridge arm, wherein a shunt resistor is arranged in the bridge arm; an evaluation device having an input connection, the evaluation device being designed to evaluate a measurement signal which is present at the input connection and which is dependent on a voltage drop across the shunt resistor, in order to determine a measured variable; and a voltage peak suppression device, which is designed to short-circuit the input connection of the evaluation device when a voltage peak occurs at the shunt resistor.

Surgical instrument with a sensing array

A surgical instrument is disclosed. The surgical instrument includes a shaft, a sensing array and a fluid detection circuit. The sensing array is positioned within the shaft. The fluid detection circuit is electrically coupled to the sensing array, and is configured to determine when a fluid originating from an environment external to the shaft is present within the shaft.

Surgical instrument comprising a control circuit

A surgical instrument is disclosed comprising a housing and a control circuit mounted to and/or embedded in the housing.

TRANSIMPEDANCE AMPLIFIER AND RECEIVER CIRCUIT FOR OPTICAL SIGNALS WITH A PHOTODIODE AND A TRANSIMPEDANCE AMPLIFIER
20220006433 · 2022-01-06 ·

A transimpedance amplifier may include a voltage-controlled operational amplifier having a non-inverting input connected to ground, an inverting input receiving a current signal to be amplified, an output coupled to the inverting input via a coupling resistor, and a power-down input (PWDN input) activated upon receipt of at least one power-down signal (PWDN) such that at least one internal current source is thereupon deactivated.

TRANSIMPEDANCE AMPLIFIER AND RECEIVER CIRCUIT FOR OPTICAL SIGNALS WITH A PHOTODIODE AND A TRANSIMPEDANCE AMPLIFIER
20220006433 · 2022-01-06 ·

A transimpedance amplifier may include a voltage-controlled operational amplifier having a non-inverting input connected to ground, an inverting input receiving a current signal to be amplified, an output coupled to the inverting input via a coupling resistor, and a power-down input (PWDN input) activated upon receipt of at least one power-down signal (PWDN) such that at least one internal current source is thereupon deactivated.

Method and apparatus for in-situ on-chip timing
11764763 · 2023-09-19 · ·

An Integrated Circuit includes a target circuit, first and second logic chains, a feedback path and calibration circuitry. The target circuit includes first and second inputs. The first and second logic chains propagate a signal from a common input point to the first and second inputs of the target circuit, respectively. The feedback path receives the signal from the first or second input and feeds the signal back to the common input point. The calibration circuitry is configured to connect the first input to the feedback path thereby forming a first closed-loop oscillator circuit, and measure a first oscillation frequency of the first closed-loop oscillator circuit, connect the second input to the feedback path, thereby forming a second closed-loop oscillator circuit, and measure a second oscillation frequency of the second closed-loop oscillator circuit, and verify a timing constraint responsively to the first and second oscillating frequencies.

Method and apparatus for in-situ on-chip timing
11764763 · 2023-09-19 · ·

An Integrated Circuit includes a target circuit, first and second logic chains, a feedback path and calibration circuitry. The target circuit includes first and second inputs. The first and second logic chains propagate a signal from a common input point to the first and second inputs of the target circuit, respectively. The feedback path receives the signal from the first or second input and feeds the signal back to the common input point. The calibration circuitry is configured to connect the first input to the feedback path thereby forming a first closed-loop oscillator circuit, and measure a first oscillation frequency of the first closed-loop oscillator circuit, connect the second input to the feedback path, thereby forming a second closed-loop oscillator circuit, and measure a second oscillation frequency of the second closed-loop oscillator circuit, and verify a timing constraint responsively to the first and second oscillating frequencies.