A flip-flop circuit includes first and second latches. The first latch comprises a first inverting logic element and a second inverting logic element. The first inverting logic element has a first logic threshold voltage. The second inverting logic element is connected in antiparallel to the first inverting logic element and has a second logic threshold voltage. The first and second logic threshold voltages are set with respect to one half of a power supply voltage. The second latch comprises a third inverting logic element and a fourth inverting logic element. The third inverting logic element is connected to the first latch and has a third logic threshold voltage. The fourth inverting logic element is connected in antiparallel to the third inverting logic element and has a fourth logic threshold voltage. The third and fourth logic threshold voltages are set with respect to one half of the power supply voltage.

An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.

A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

The present disclosure presents various systems and methods for implementing a physical unclonable function device. One such method comprises providing an integrated circuit having a plurality of set/reset flip flop logic circuits, wherein each of the set/reset flip flop logic circuits enters a metastable state for a particular input sequence. The method includes varying circuit parameters for each of the plurality of set/reset flip flop logic circuits to account for manufacturing variations in the set/reset flip flop logic circuits and enable generating a stable but random output in response to the particular input sequence. Thus, by applying the particular input sequence to the integrated circuit, a unique identifier for the integrated circuit can be derived from an output response of the plurality of set/reset flip flop logic circuits.

A detection circuit configured to detect whether timing violations occur in a target circuit. The target circuit is operated according a clock signal. The detection circuit includes a signal generation circuit, a first delay adjustable circuit, a second delay adjustable circuit, and a signal detector. The signal generation circuit is configured to generate a test signal. The first and second delay adjustable circuit are respectively configured to delay the test signal and clock signal to generate a first delay signal and a second delay signal according to the operating speed of the target circuit. The signal detector is configured to generate an indicating signal according to the first delay signal, the second delay signal, the test signal, and the clock signal. The indicating signal is configured to indicate whether an operating voltage of the target circuit causes a hold time violation of timing violations to occur in the target circuit.

A flip-flop circuit comprises a pass gate, a feedback inverter, and an interleaved filter. The pass gate comprises a clock input and an inverting clock input. The feedback inverter includes a feedback input coupled to both the clock input and the inverting clock input of the pass gate. The interleaved filter comprises a delay circuit including a delay output, a C-gate element, and a blocking inverter. The C-gate element includes a C-gate input and a C-gate output. The C-gate input is coupled to the delay output of the delay circuit and the pass gate, and the C-gate output is coupled to the feedback input of the feedback inverter. The blocking inverter includes a blocking input and a blocking output. The blocking input is coupled to the delay output of the delay circuit, and the blocking output is coupled to the feedback input of the feedback inverter.

A latch device includes a differential pair, a differential circuit, and a clock gate circuit. The differential pair receives differential input signals, and the differential circuit performs a logic operation on the differential input signals. The clock gate circuit is configured to supply a supply voltage from the power supply node to the first connection node according to a clock signal. The clock gate circuit includes a reference-independent circuit and a reference-dependent circuit. The reference-independent circuit is configured to control a first electrical path between the power supply node and the first connection node according to the clock signal. The reference-dependent circuit is configured to control a second electrical path between the power supply node and the first connection node according to the clock signal and a first control signal, wherein the first control signal is determined according to a voltage level of one of the differential input signals.

A data synthesizer includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to latch a first data under control of a first latch clock signal. The second input circuit is configured to latch a second data under control of the first latch clock signal. A phase of the first data is the same as a phase of the second data. The output circuit is connected to the first input circuit and the second input circuit. The output circuit is configured to output the first data and the second data in sequence.

A flip-flop circuit includes first and second latches. The first latch comprises a first inverting logic element and a second inverting logic element. The first inverting logic element has a first logic threshold voltage. The second inverting logic element is connected in antiparallel to the first inverting logic element and has a second logic threshold voltage. The first and second logic threshold voltages are set with respect to one half of a power supply voltage. The second latch comprises a third inverting logic element and a fourth inverting logic element. The third inverting logic element is connected to the first latch and has a third logic threshold voltage. The fourth inverting logic element is connected in antiparallel to the third inverting logic element and has a fourth logic threshold voltage. The third and fourth logic threshold voltages are set with respect to one half of the power supply voltage.

A semiconductor device and a method of operating a semiconductor device are provided. The semiconductor device includes a first latching circuit and a second latching circuit coupled to the first latching circuit. The second latching circuit includes a first feedback circuit and a first transmission circuit, the first feedback circuit configured to receive a first clock signal of a first phase and a second clock signal of a second phase, and the first transmission circuit configured to receive the second clock signal and a third clock signal of a third phase. The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.