A semiconductor device includes: a first latch circuit that includes a first inverting circuit, a second inverting circuit, a third inverting circuit, and a fourth inverting circuit; a first first-type well region; a second first-type well region; and a second-type well region. In a plan view, a distance between a drain of a first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the third inverting circuit is longer than a distance between the drain of the first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the fourth inverting circuit.

A data synthesizer includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to latch a first data under control of a first latch clock signal. The second input circuit is configured to latch a second data under control of the first latch clock signal. A phase of the first data is the same as a phase of the second data. The output circuit is connected to the first input circuit and the second input circuit. The output circuit is configured to output the first data and the second data in sequence.

A level shifter can achieve a level shift by a wide margin. The level shifter includes a latch circuit, a clamping circuit, a protection circuit, and an input circuit. The latch circuit is coupled between a high-voltage terminal and a pair of output terminals for outputting a pair of output signals. The clamping circuit is coupled between a medium-voltage terminal and the pair of output terminals and limits the minimum voltage of the pair of output signals to the medium voltage. The protection circuit is set between the latch circuit and the input circuit, and prevents an excessive voltage drop between the input circuit and the pair of output terminals. The input circuit includes an input transistor pair coupled between the protection circuit and a low-voltage terminal having a low voltage. The input transistor pair receives a pair of input signals and operates accordingly.

According to one general aspect, an apparatus may include a latch circuit configured to, depending in part upon a state of an enable signal, substantially pass the first clock signal to an output signal. The latch circuit may include at least two transistors configured to essentially perform a NAND function and controlled by a second clock signal, wherein the at least two transistors are configured to alter the timing of the substantial passing of the first clock signal to the output signal.

The present disclosure presents various systems and methods for implementing a physical unclonable function device. One such method comprises providing an integrated circuit having a plurality of set/reset flip flop logic circuits, wherein each of the set/reset flip flop logic circuits enters a metastable state for a particular input sequence. The method includes varying circuit parameters for each of the plurality of set/reset flip flop logic circuits to account for manufacturing variations in the set/reset flip flop logic circuits and enable generating a stable but random output in response to the particular input sequence. Thus, by applying the particular input sequence to the integrated circuit, a unique identifier for the integrated circuit can be derived from an output response of the plurality of set/reset flip flop logic circuits.

A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

A pulse-based flip flop circuit includes; a pulse generator generating a pulse signal and an inverted pulse signal, a scan hold buffer holding a scan input signal for a delay time, and a latch circuit including an intermediate node receiving one of a data signal and the scan input signal in response to a scan enable signal, the pulse signal and the inverted pulse signal. The pulse generator circuit includes; a direct path providing a clock signal as a direct path input to a NAND circuit, a delay path including a number of stages configured to delay the clock signal and provide a delayed clock signal as a delay path input to NAND circuit, wherein the NAND circuit performs a NAND operation on the direct path input and the delay path input to generate the inverted pulse signal, and a feedback path providing the pulse signal to a first stage among the number of stages of the delay path.

A circuit includes first and second power nodes having differing first and second voltage levels, and a reference node having a reference voltage level. A master latch outputs a first data bit based on a received data bit; a slave latch includes a first inverter that outputs a second data bit based on the first data bit and a second inverter that outputs an output data bit based on a selected one of the first data bit or a third data bit; a level shifter outputs the third data bit based on a fourth data bit; and a retention latch outputs the fourth data bit based on the second data bit. The first and second inverters and the level shifter are coupled between the first power node and the reference node, and the retention latch includes a plurality of transistors coupled between the second power node and the reference node.

A circuit for mitigating single-effect-transients (SETs) comprising: a first sub-circuit comprising a first p-type transistor arrangement configured to generate a first output and a first n-type transistor arrangement configured to generate a second output; and a second sub-circuit comprising a connecting p-type transistor arrangement and a connecting n-type transistor arrangement connected in series, wherein the first output and the second output are electrically coupled to each other through the second sub-circuit.

One example of the present disclosure is an integrated circuit (IC). The IC includes an inverter with an input and an output, a clock transmission gate coupled to the output of the inverter; and a plurality of storage cells. The clock transmission gate is coupled to each of the plurality of storage cells, wherein each of the plurality of storage cells comprises a plurality of nodes arranged based on a minimum spacing.