The control system comprises an amplifier (264; 266) designed to receive an input control signal (cmd*; cmd*), in order to amplify the input control signal (cmd*; cmd*) so as to obtain an output control signal (CMD*; CMD*) and to apply the output control signal (CMD*; CMD*) to the switch (222; 224) in order to either open or close the switch (222; 224), the amplifier (264; 266) having two, positive and negative, supply terminals intended to receive a supply voltage. It moreover comprises an inhibiting device (310; 314) for the amplifier (264; 266) designed to lower the supply voltage on receiving what is referred to as a total inhibit control (INHIB_T) so that the output control signal (CMD*; CMD*) keeps the switch (222; 224) open irrespective of the input control signal (cmd*; cmd*).

A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.

In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.

The present disclosure relates to driver circuitry for driving a piezoelectric transducer. The circuitry comprises: output stage circuitry configured to receive an input signal and to drive the piezoelectric transducer to produce the output signal; variable voltage power supply circuitry configured to output a supply voltage for the charge drive output stage circuitry, wherein the supply voltage output by the variable voltage power supply circuitry varies based on the input signal; a supply capacitor for receiving the supply voltage output by the variable voltage power supply circuitry; a reservoir capacitor; and circuitry for transferring charge between the reservoir capacitor and the supply capacitor.

A semiconductor circuit includes a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal. A second logic gate that receives inputs of the first output signal of the first logic gate, the clock signal, and an inverted output signal of the first input signal and performs a second logical operation to output the feedback signal.

Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.

Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.

A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

A system and method for digital signal reception comprise outputting first and second digital transmission signals complementary to each other. Further, a first and second output signals are outputted. The first output signal has a logical value based on a product of a logical value of the first digital transmission signal and a logical value complementary to a logical value of the second digital transmission signal is outputted. The second output signal has a logical value based on a sum of a logical value complementary to the logical value of the first digital transmission signal and the logical value of the second digital transmission signal.

A system and method for digital signal reception comprise outputting first and second digital transmission signals complementary to each other. Further, a first and second output signals are outputted. The first output signal has a logical value based on a product of a logical value of the first digital transmission signal and a logical value complementary to a logical value of the second digital transmission signal is outputted. The second output signal has a logical value based on a sum of a logical value complementary to the logical value of the first digital transmission signal and the logical value of the second digital transmission signal.