A microcontroller is coupled to a detection circuit which generates a detection signal. The microcontroller includes a processing circuit and an input-output circuit. The processing circuit generates an output signal according to the detection signal. In response to the output signal being at a specific level, the processing circuit enables a reset signal. The input-output circuit includes a latch circuit and a counter circuit. The latch circuit latches the output signal to generate a latched signal. The counter circuit starts adjusting the count value in response to the reset signal being enabled. The counter circuit changes the level of the latched signal in response to the count value being equal to a predetermined value.

A microcontroller is coupled to a detection circuit which generates a detection signal. The microcontroller includes a processing circuit and an input-output circuit. The processing circuit generates an output signal according to the detection signal. In response to the output signal being at a specific level, the processing circuit enables a reset signal. The input-output circuit includes a latch circuit and a counter circuit. The latch circuit latches the output signal to generate a latched signal. The counter circuit starts adjusting the count value in response to the reset signal being enabled. The counter circuit changes the level of the latched signal in response to the count value being equal to a predetermined value.

Systems and methods for propagating control signals in memories are described. One implementation includes a plurality of logic gates and a latch coupled between a control signal input and a delay line. The latch may store the value of the control signal before the control signal floats, thereby reducing the risk of incorrect signal propagation. Furthermore, the implementation may also include a clamp signal that isolates the plurality of logic gates before the control signal floats and continues to isolate the plurality of logic gates until after the control signal returns to either a digital one or a digital zero. The clamp signal may reduce leakage by disconnecting transistors within the logic gates from their power supply.

This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample an output of a storage element. The system can include a mono-shot circuit configured to monitor the output of the storage element and generate a pulse when the monitored output of the storage element differs from the sampled output. The system can include a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch signal in response to the pulse from the mono-shot circuit. The system can include an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the drive circuit, and to generate an error signal when the sampled output differs from the glitch signal.

This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample an output of a storage element. The system can include a mono-shot circuit configured to monitor the output of the storage element and generate a pulse when the monitored output of the storage element differs from the sampled output. The system can include a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch signal in response to the pulse from the mono-shot circuit. The system can include an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the drive circuit, and to generate an error signal when the sampled output differs from the glitch signal.