Aggressor rows may be detected by comparing access count values of word lines to a threshold value. Based on the comparison, a word line may be determined to be an aggressor row. The threshold value may be dynamically generated, such as a random number generated by a random number generator. In some examples, a random number may be generated each time an activation command is received. Responsive to detecting an aggressor row, a targeted refresh operation may be performed.

A fluctuating oscillator includes: an adder that has an input terminal to which an input signal including a main signal and an uncorrelated signal that is uncorrelated with the main signal and is higher in frequency than the main signal is input, and adds a feedback signal to the input signal; a threshold discrimination unit that generates a pulse signal by comparing an addition signal added by the adder with a threshold; a transient response unit that generates an output signal by transiently responding the generated pulse signal; and a feedback loop that feeds back the output signal to the adder as the feedback signal.

A fluctuating oscillator includes: a processor including a digital circuit, and the processor includes a random variable generation unit that generates a random variable, a lookup table that stores a waveform signal in advance, a computation unit that imparts fluctuation to the waveform signal based on the waveform signal read from the lookup table, the random variable generated by the random variable generation unit, and a pulse signal to be fed back, a threshold discrimination unit that generates a pulse signal by comparing a fluctuating signal output from the computation unit with a predetermined threshold, and a feedback loop that causes the pulse signal to be fed back to the computation unit.

A noise reduction circuit for a matrix LED driver includes a pseudo random number generator, an up counter, a clock module, and a plurality of matrix switch controllers. The matrix switch controllers and the up counter randomly change a power-on sequence applied across matrix switches in the matrix LED driver according to working random numbers generated by the pseudo random number generator. The circuit prevents jitter-induced noise from periodically reoccurring at the power source of the matrix LED driver, thereby reducing noise energy.

A noise reduction circuit for a matrix LED driver includes a pseudo random number generator, an up counter, a clock module, and a plurality of matrix switch controllers. The matrix switch controllers and the up counter randomly change a power-on sequence applied across matrix switches in the matrix LED driver according to working random numbers generated by the pseudo random number generator. The circuit prevents jitter-induced noise from periodically reoccurring at the power source of the matrix LED driver, thereby reducing noise energy.

A random bit circuit includes four storage cells controlled by four different word lines. The first storage cell and the second storage cell are disposed along a first direction sequentially, and the first storage cell and the third storage cell are disposed along a second direction sequentially. The third storage cell and the fourth storage cell are disposed along the first direction sequentially. The first storage cell and the fourth storage cell are coupled in series, and the second storage cell and the third storage cell are coupled in series.

A random bit circuit includes four storage cells controlled by four different word lines. The first storage cell and the second storage cell are disposed along a first direction sequentially, and the first storage cell and the third storage cell are disposed along a second direction sequentially. The third storage cell and the fourth storage cell are disposed along the first direction sequentially. The first storage cell and the fourth storage cell are coupled in series, and the second storage cell and the third storage cell are coupled in series.

A random bit generator includes a voltage source, a bit data cell, and a sensing control circuit. The voltage source provides a scan voltage during enroll operations. The data cell includes a first transistor and a second transistor. The first transistor has a first terminal coupled to a first bit line, a second terminal coupled to the voltage source, and a control terminal. The second transistor has a first terminal coupled to a second bit line, a second terminal coupled to the voltage source, and a control terminal. The sensing control circuit is coupled to the first bit line and the second bit line, and outputs a random bit data according to currents generated through the first transistor and the second transistor during an enroll operation of the bit data cell.

A random bit generator includes a voltage source, a bit data cell, and a sensing control circuit. The voltage source provides a scan voltage during enroll operations. The data cell includes a first transistor and a second transistor. The first transistor has a first terminal coupled to a first bit line, a second terminal coupled to the voltage source, and a control terminal. The second transistor has a first terminal coupled to a second bit line, a second terminal coupled to the voltage source, and a control terminal. The sensing control circuit is coupled to the first bit line and the second bit line, and outputs a random bit data according to currents generated through the first transistor and the second transistor during an enroll operation of the bit data cell.

A random number generator including: a first ring oscillator including a first inverter chain, the first inverter chain including a plurality of serially connected first inverters, the first ring oscillator configured to output a first random signal generated at a first sub-node between two neighboring first inverters among the plurality of first inverters; a second ring oscillator including a second inverter chain, the second inverter chain including a plurality of serially connected second inverters, the second ring oscillator configured to output a second random signal generated at a second sub-node between two neighboring second inverters among the plurality of second inverters; and a signal processing circuit for generating a random number by combining the first random signal with the second random signal.