Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.

Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.

In an embodiment a switching power supply includes a voltage ramp generator comprising at least one output capacitor, wherein the generator is configured such that the output capacitor has a first value during a first operating cycle of a first operating mode and a second value during subsequent operating cycles of the first operating mode.

An improved ramp generator enables a very high degree of linearity in an output voltage ramp signal. Output ramps of the output voltage ramp signal are alternatingly produced from two preliminary ramp signals during alternating time periods. Preliminary ramps are produced at different preliminary ramp nodes that are alternatingly connected to an output node. The preliminary ramps continuously ramp during and in some cases beyond, e.g., before and/or after, the time periods. In some embodiments, switches alternatingly connect two capacitors to at least one current source, a reset voltage source, and the output node to alternatingly produce the preliminary ramps.

An improved ramp generator enables a very high degree of linearity in an output voltage ramp signal. Output ramps of the output voltage ramp signal are alternatingly produced from two preliminary ramp signals during alternating time periods. Preliminary ramps are produced at different preliminary ramp nodes that are alternatingly connected to an output node. The preliminary ramps continuously ramp during and in some cases beyond, e.g., before and/or after, the time periods. In some embodiments, switches alternatingly connect two capacitors to at least one current source, a reset voltage source, and the output node to alternatingly produce the preliminary ramps.

An improved ramp generator enables a very high degree of linearity in an output voltage ramp signal. Output ramps of the output voltage ramp signal are alternatingly produced from two preliminary ramp signals during alternating time periods. Preliminary ramps are produced at different preliminary ramp nodes that are alternatingly connected to an output node. The preliminary ramps continuously ramp during and in some cases beyond, e.g., before and/or after, the time periods. In some embodiments, switches alternatingly connect two capacitors to at least one current source, a reset voltage source, and the output node to alternatingly produce the preliminary ramps.

An improved ramp generator enables a very high degree of linearity in an output voltage ramp signal. Output ramps of the output voltage ramp signal are alternatingly produced from two preliminary ramp signals during alternating time periods. Preliminary ramps are produced at different preliminary ramp nodes that are alternatingly connected to an output node. The preliminary ramps continuously ramp during and in some cases beyond, e.g., before and/or after, the time periods. In some embodiments, switches alternatingly connect two capacitors to at least one current source, a reset voltage source, and the output node to alternatingly produce the preliminary ramps.

In start-up, current is sourced by a current source to a first plate of a first capacitor while a second capacitor is maintained at zero charge. In a subsequent first operating phase, current is sourced to a first plate of the second capacitor while a second plate of the first capacitor is connected to the first plate of the second capacitor. At the end of the first operating phase, the first capacitor is discharged. In a subsequent second operating phase, current is sourced to the first plate of the first capacitor while a second plate of the second capacitor is connected to the first plate of the first capacitor. At the end of the second operating phase, the second capacitor is discharged. Steady state operation of the circuit involves an alternation of the first and second operating phases interleaved with transition phases where the first and second capacitors are discharged.

In start-up, current is sourced by a current source to a first plate of a first capacitor while a second capacitor is maintained at zero charge. In a subsequent first operating phase, current is sourced to a first plate of the second capacitor while a second plate of the first capacitor is connected to the first plate of the second capacitor. At the end of the first operating phase, the first capacitor is discharged. In a subsequent second operating phase, current is sourced to the first plate of the first capacitor while a second plate of the second capacitor is connected to the first plate of the first capacitor. At the end of the second operating phase, the second capacitor is discharged. Steady state operation of the circuit involves an alternation of the first and second operating phases interleaved with transition phases where the first and second capacitors are discharged.

An apparatus includes a first transistor including a first gate, a first drain and a first source. A second transistor includes a second gate and a second source, the second gate is coupled to a first current source configured to generate a linear current ramp, the second source is coupled to the first gate and a second current source configured to generate a constant current through the second transistor determined by a sampled voltage between the first gate and the first source. A third transistor includes a third gate and a third source, the third gate is coupled to the first drain, and the third source is coupled to an inductive load, wherein the third transistor is configured to source a load current to the inductive load in response to an integration of the linear current ramp. A first capacitor is coupled between the third source and the second gate.