Disclosed is an auto-calibration circuit and method to generate the precise pulses that are required for energy savings achieved by using wide-band resonating cells for digital circuits. The calibration circuit performs a calibration technique by programming the number of PMOS devices and NMOS devices in parallel to an inverter, and these numbers are dynamically changed based on a target reference voltage that is defined by a resistance ratio or any PVT-independent reference voltages could also be set as a target voltage level.

Some embodiments include a resonant converter klystron driver. A resonant converter klystron driver, for example, may include an input power supply; a full-bridge circuit coupled with the input power supply; a resonant circuit coupled with the full-bridge; a step-up transformer coupled with the resonant circuit; a rectifier coupled with a step-up transformer; a filter stage coupled with the rectifier; and an output coupled with the filter stage. In some embodiments, the output could be coupled with a klystron.

An embodiment pulse generator circuit comprises a first electronic switch coupled between first and second nodes, and a second electronic switch coupled between the second node and a reference node. An LC resonant circuit comprising an inductance and a capacitance is coupled between the first and reference nodes along with charge circuitry comprises a further inductance in a current flow line between a supply node and an intermediate node in the LC resonant circuit. Drive circuitry of the electronic switches repeats, during a sequence of switching cycles, charge time intervals, wherein the capacitance in the LC resonant circuit is charged via the charge circuit, and pulse generation time intervals, wherein a pulsed current is provided to the load via the first and second nodes. The charge and pulse generation time intervals are interleaved with oscillation time intervals where the LC resonant circuit oscillates at a resonance frequency.

An embodiment pulse generator circuit comprises a first electronic switch coupled between first and second nodes, and a second electronic switch coupled between the second node and a reference node. An LC resonant circuit comprising an inductance and a capacitance is coupled between the first and reference nodes along with charge circuitry comprises a further inductance in a current flow line between a supply node and an intermediate node in the LC resonant circuit. Drive circuitry of the electronic switches repeats, during a sequence of switching cycles, charge time intervals, wherein the capacitance in the LC resonant circuit is charged via the charge circuit, and pulse generation time intervals, wherein a pulsed current is provided to the load via the first and second nodes. The charge and pulse generation time intervals are interleaved with oscillation time intervals where the LC resonant circuit oscillates at a resonance frequency.

A method of generating a high-power Radio-Frequency ultrashort waveform comprising the steps of generating an input waveform at a relatively low power level from an impulse response characteristic of a reverberant cavity via one-bit quantization and time reversal; generating an amplified input waveform of a power higher than the input waveform via feeding the input waveform into one or more amplifiers; generating a compressed ultrashort pulse having a high power relative to the amplified input waveform via feeding the amplified input waveform into the reverberant cavity.

A method of generating a high-power Radio-Frequency ultrashort waveform comprising the steps of generating an input waveform at a relatively low power level from an impulse response characteristic of a reverberant cavity via one-bit quantization and time reversal; generating an amplified input waveform of a power higher than the input waveform via feeding the input waveform into one or more amplifiers; generating a compressed ultrashort pulse having a high power relative to the amplified input waveform via feeding the amplified input waveform into the reverberant cavity.

A semiconductor device includes an output switching device having an input node, an output node, and a control input node. The control input node enables an input voltage applied to the input node to be switched to the output node. A gate pull-down circuit controls the control input node of the output switching device in response to at least one control signal. The gate pull-down circuit activates the output switching device by raising the voltage level of the control input node above the voltage level of the output node and deactivates the output switching device by clamping the control input node to the voltage level of the output node. A gate pull-up circuit receives an enable signal and generates the at least one control signal to the gate pull-down circuit in response to the enable signal.

A semiconductor device includes an output switching device having an input node, an output node, and a control input node. The control input node enables an input voltage applied to the input node to be switched to the output node. A gate pull-down circuit controls the control input node of the output switching device in response to at least one control signal. The gate pull-down circuit activates the output switching device by raising the voltage level of the control input node above the voltage level of the output node and deactivates the output switching device by clamping the control input node to the voltage level of the output node. A gate pull-up circuit receives an enable signal and generates the at least one control signal to the gate pull-down circuit in response to the enable signal.

The driver circuit comprises a first node (J1), which is connected to a first terminal of the Pockels cell (CP), a second node (J2), which is connected to a second terminal of the Pockels cell (CP), wherein the first node (J1) is connected to a first potential (+HV) via a first switching unit (S1) and the second node (J2) is connected to the first potential (+HV) via a second switching unit (S2) and wherein the first node (J1) is connected to a second potential (HV) via a first resistance (R1) and the second node (J2) is connected to the second potential (HV) via a second resistance (R2); and wherein the first node (J1) is connected to the second node (J2) via a series circuit comprising a third resistance (R3) and an inductance (L1).

The driver circuit comprises a first node (J1), which is connected to a first terminal of the Pockels cell (CP), a second node (J2), which is connected to a second terminal of the Pockels cell (CP), wherein the first node (J1) is connected to a first potential (+HV) via a first switching unit (S1) and the second node (J2) is connected to the first potential (+HV) via a second switching unit (S2) and wherein the first node (J1) is connected to a second potential (HV) via a first resistance (R1) and the second node (J2) is connected to the second potential (HV) via a second resistance (R2); and wherein the first node (J1) is connected to the second node (J2) via a series circuit comprising a third resistance (R3) and an inductance (L1).