Disclosed is a receiving circuit, which includes a hysteresis detector that receives an input signal corresponding to a first voltage level and outputs a detection signal having a first threshold voltage and a second threshold voltage, and a level shifter that receives the detection signal, converts the first voltage level of the detection signal to a second voltage level higher than the first voltage level so as to be output as an output signal, and outputs a feedback signal of the second voltage level, and the hysteresis detector receives the feedback signal from the level shifter and adjusts the first threshold voltage and the second threshold voltage based on the feedback signal.

An electronic assembly including a plurality of electrically conductive elements separated by insulative material and a digital FM demodulator circuit coupled to some of the electrically conductive elements. The FM demodulator circuit having an FM detector circuit and a DC drift reducing circuit. The FM detector circuit has a detector input and a detector output that is the output of a comparator that is AC coupled to the rest of the FM detector circuit, the detector input receiving an input signal. The DC drift reducing circuit is electrically coupled to the detector output of the comparator, the DC drift reducing circuit detecting a DC drift of the detector output, the DC drift reducing circuit being additionally coupled to an input of the comparator, the DC drift reducing circuit substantially eliminating DC drift at the output of the FM demodulator circuit.

A comparator includes a current mirror module, a comparison module and a buffering and outputting module. The current mirror module provides a bias current to the comparison module. The comparison module comprises a positive input end, a first negative input end and a second negative input end, the positive input end connects to an external terminal, the first negative input end and the second negative input end input a low threshold voltage and a high threshold voltage, respectively. The comparison module compares a voltage of the positive input end to the low threshold voltage and the high threshold voltage, and outputs a comparison result to the buffering and outputting module.

A clock signal synchronization circuit includes a delay line configured to delay an input clock signal in response to a delay control signal to output an output clock signal, a replica circuit configured to delay the output clock signal to output a feedback clock signal, a phase detector configured to compare the input clock signal and the feedback clock signal with each other to detect a phase difference, and a delay control circuit configured to generate the delay control signal based on the phase difference. The replica circuit may delay the output clock signal based on an operation mode of a memory device to output the feedback clock signal.

A contact detector circuit that detects a change in a DC sensor signal based on a change in a physical amount to be detected includes: a reference signal generation circuit that generates a reference signal based on the DC sensor signal; a trigger signal output circuit that compares the DC sensor signal with the reference signal and outputs a trigger signal based on a result of the comparison; and a sampling-and-holding circuit that holds the reference signal when the trigger signal is started to be outputted and outputs the held reference signal to the trigger signal output circuit while the trigger signal is outputted. The trigger signal output circuit uses the reference signal outputted by the sampling-and-holding circuit for the comparison with the DC sensor signal while the trigger signal is outputted.

The present invention discloses a comparator and low power consumption oscillator thereof. Wherein, the comparator comprises a current mirror module, a comparison module and a buffering and outputting module, the low power consumption oscillator comprises a capacitor, a current bias module, a switch module and the comparator, the comparison module comprises a positive input end, a first negative input end and a second negative input end, the capacitor connects to the positive input end of the comparator, when a voltage of the capacitor is less than a low threshold voltage of the first negative input end of the comparator, the comparator outputs a low voltage to the switch module, which controls the current bias module to charge the capacitor, when a voltage of the capacitor is greater than a high threshold voltage of the second negative input end of the comparator, the comparator outputs a high voltage to the switch module, which controls the current bias module to discharge the capacitor, thus, through one comparator, a periodic charging and discharging to the capacitor is achieved, and an oscillation signal is output, thus a number of the comparators is reduced, a structure of the circuit is simplified, a power consumption of the circuit and a cost of a product is reduced.

A phase interpolator includes differential pairs, a switching circuit, an output stage, and a correction circuit. The differential pairs generate a first signal and a second signal according to a first group of input signals and a second group of input signals. The switching circuit is turned on or turned off, according to control signals, to transmit the first signal and the second signal to a current source circuit, in order to control a value of the first signal and a value of the second signal. The output stage generates a first output signal according to the first signal and the second signal. The correction circuit provides and stables a common mode voltage of the first output signal according to the first output signal.

A leakage mitigation circuit is provided. The leakage mitigation circuit includes an inverter coupled to a storage node, wherein the storage node receives a signal output by an imaging pixel having a first voltage level to be stored. The inverter inverts the signal to a second voltage level. A single transistor coupled to the inverter and the storage node inverts the signal output by the inverter to the first level to hold the signal at the storage node to its original level. A self-biased device coupled to the inverter lowers current disturbance related to the storage node and increase threshold voltage at which fluctuation of the level of the signal at the storage node causes the signal to be inverted by the inverter.

A leakage mitigation circuit is provided. The leakage mitigation circuit includes an inverter coupled to a storage node, wherein the storage node receives a signal output by an imaging pixel having a first voltage level to be stored. The inverter inverts the signal to a second voltage level. A single transistor coupled to the inverter and the storage node inverts the signal output by the inverter to the first level to hold the signal at the storage node to its original level. A self-biased device coupled to the inverter lowers current disturbance related to the storage node and increase threshold voltage at which fluctuation of the level of the signal at the storage node causes the signal to be inverted by the inverter.

A clock signal synchronization circuit includes a delay line configured to delay an input clock signal in response to a delay control signal to output an output clock signal, a replica circuit configured to delay the output clock signal to output a feedback clock signal, a phase detector configured to compare the input clock signal and the feedback clock signal with each other to detect a phase difference, and a delay control circuit configured to generate the delay control signal based on the phase difference. The replica circuit may delay the output clock signal based on an operation mode of a memory device to output the feedback clock signal.