A trigger signal provided via a pulse-per-second input port of a network interface controller is detected. In response to the trigger signal, an internal hardware clock value of the network interface controller is recorded. The recorded internal hardware clock value is reported, wherein the reported internal hardware clock value is reported for use in determining a timing error of the network interface controller based at least in part on a comparison with a time value of another device that also received the trigger signal.

A trigger signal provided via a pulse-per-second input port of a network interface controller is detected. In response to the trigger signal, an internal hardware clock value of the network interface controller is recorded. The recorded internal hardware clock value is reported, wherein the reported internal hardware clock value is reported for use in determining a timing error of the network interface controller based at least in part on a comparison with a time value of another device that also received the trigger signal.

A level shifter includes a control circuit and a bias circuit. The control circuit receives a bias voltage, a first signal associated with a first voltage domain, and supply voltages associated with a second voltage domain, and outputs a second signal that is associated with the second voltage domain. The bias circuit generates the bias voltage that is indicative of the duty cycle of the second signal, and provides the bias voltage to the control circuit to control the duty cycle of the second signal. The duty cycle of the second signal is controlled such that a difference between a duty cycle of the first signal and an inverse of the duty cycle of the second signal is less than a tolerance limit.

Routines and methods disclosed herein can increase a power efficiency of a prosthetic hand without drastically reducing the speed at which it operates. A prosthesis can implement an acceleration profile, which can reduce an energy consumption of a motor, or an amount of electrical and/or mechanical noise produced by a motor, as the motor transitions from an idle state to a non-idle state. A prosthesis can implement a deceleration profile, which can reduce the energy consumption of the motor, or an amount of electrical and/or mechanical noise produced by a motor, as the motor transitions from a non-idle state to an idle state.

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input clock signal. A duty phase interpolator circuit may be coupled to the clock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals. A duty cycle adjuster circuit may be coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected clock signal responsive thereto. A duty cycle detector may be coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to correct the duty cycle error.

The signal generator includes the following: an oscillation generation circuit, configured to generate an initial oscillation signal based on an oscillation control signal; a duty cycle correction circuit, connected to an output end of the oscillation generation circuit and configured to adjust a duty cycle of the initial oscillation signal based on a duty cycle control signal, to generate an adjusted oscillation signal; an output interface, connected to an output end of the duty cycle correction circuit and configured to output the adjusted oscillation signal to an external test system; and an amplitude adjustment circuit, connected to the output end of the duty cycle correction circuit and configured to adjust an amplitude of the adjusted oscillation signal based on an amplitude control signal, to generate a test signal.

One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

A signal detection system and a memory detection method are provided. The system includes a signal generator, generating a reference test signal based on an external parameter, the reference test signal being a clock signal satisfying a preset duty cycle, where a duty cycle test is performed on the reference test signal based on a test circuit, to determine whether a function of the test circuit is normal. If the function of the test circuit is normal, different portions under test are sequentially selected based on a test control signal, and the duty cycle test is performed, based on the test circuit, on a signal outputted by each of the selected portions under test. The portions under test include a signal converter and a write clock path.

Systems and methods are disclosed for differential clock duty cycle correction. For example, a method includes converting an input rail-to-rail differential clock signal to a low-swing differential signal; fixing a DC bias level of the low-swing differential signal; changing DC bias levels of ends of the low-swing differential signal in a complementary manner to change cross-over points of the low-swing differential signal; and inputting the low-swing differential signal to a level shifter and buffer to generate a duty-corrected rail-to-rail digital differential clock signal. For example, an apparatus may include a differential pair of CMOS transmission-gate switches as clock input switches; complementary differential pairs of transistors with gate terminals connected to a differential control voltage signal; and/or extra current sources for independently controlling the DC bias voltages of ends of a differential clock signal.

Design and methods for implementing a Rational Ratio Multiplier (RRM) with close to 50% duty cycle. This invention gives an optimal way to implement RRM that save both area and power for a given design and able to achieve a good accuracy of the output clock with a difference between the high period and the low period of the output clock by only half a cycle of the input clock which is the closest to get to 50% duty cycle clock.