A clock selector circuit receives a first input clock signal (CLK1) having a first frequency, and a second input clock signal (CLK2) having a second frequency. A phase difference detector is configured to detect when a phase difference occurs, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using when a clock edge crosses zero, and to signal this zero crossing to switching circuitry. The switching circuitry is configured, in response to receiving a zero-crossing signal from the phase difference detector, to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch an output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).

A clock selector circuit receives a first input clock signal (CLK1) having a first frequency, and a second input clock signal (CLK2) having a second frequency. A phase difference detector is configured to detect when a phase difference occurs, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using when a clock edge crosses zero, and to signal this zero crossing to switching circuitry. The switching circuitry is configured, in response to receiving a zero-crossing signal from the phase difference detector, to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch an output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).

A method and apparatus for enhancing the sensitivity of an oscillator circuit functioning, in use, to sense changes in the inductance of inductive elements and/or the capacitance of capacitive elements coupled to said oscillator circuit. The oscillator circuit is coupled to a nonlinear resonator for generating a comb of frequencies in response to a drive frequency generated by the oscillator circuit, the comb of frequencies having at least a portion of at least one tooth for which an absolute value of the first derivative of the drive frequency with respect to said comb frequency is less than 1.0, comparing an output of the nonlinear resonator with an output of a reference oscillator for detecting changes in the drive signal of the oscillator circuit as enhanced by the slope of the at least a portion of at least one tooth for which the absolute value of the first derivative of the drive frequency with respect to said comb frequency is less than 1.0.

A method and apparatus for enhancing the sensitivity of an oscillator circuit functioning, in use, to sense changes in the inductance of inductive elements and/or the capacitance of capacitive elements coupled to said oscillator circuit. The oscillator circuit is coupled to a nonlinear resonator for generating a comb of frequencies in response to a drive frequency generated by the oscillator circuit, the comb of frequencies having at least a portion of at least one tooth for which an absolute value of the first derivative of the drive frequency with respect to said comb frequency is less than 1.0, comparing an output of the nonlinear resonator with an output of a reference oscillator for detecting changes in the drive signal of the oscillator circuit as enhanced by the slope of the at least a portion of at least one tooth for which the absolute value of the first derivative of the drive frequency with respect to said comb frequency is less than 1.0.

A class D amplifier circuit receives an analog audio signal with a first reference voltage as its center level, and outputs an output pulse signal having a duty cycle that corresponds to the analog audio signal. A bias circuit generates a second reference voltage having a voltage level obtained as a division of the first reference voltage and the power supply voltage. A periodic voltage generating circuit of the class D amplifier circuit generates a periodic voltage having a triangle waveform or otherwise a sawtooth waveform having an amplitude that corresponds to the second reference voltage.

A class D amplifier circuit receives an analog audio signal with a first reference voltage as its center level, and outputs an output pulse signal having a duty cycle that corresponds to the analog audio signal. A bias circuit generates a second reference voltage having a voltage level obtained as a division of the first reference voltage and the power supply voltage. A periodic voltage generating circuit of the class D amplifier circuit generates a periodic voltage having a triangle waveform or otherwise a sawtooth waveform having an amplitude that corresponds to the second reference voltage.

Implementations of conductive energy weapons (CEWs) may include a shock generating circuit configured to couple to a power source, two electrodes operatively coupled to the shock generating circuit, and a safety circuit operatively coupled to the shock generating circuit. The shock generating circuit may be configured to generate a first pulse train and deliver the first pulse train to a target, and may be configured to generate at least a second pulse train and deliver the at least second pulse train to a target. The safety circuit may be configured to prevent the CEW from applying pulse trains to the target after a predetermined number of pulse trains. The first pulse train may include two or more pulses having waveforms substantially identical with each other, each of the waveforms of the two or more pulses having both a positive voltage segment and a negative voltage segment.

Implementations of conductive energy weapons (CEWs) may include a shock generating circuit configured to couple to a power source, two electrodes operatively coupled to the shock generating circuit, and a safety circuit operatively coupled to the shock generating circuit. The shock generating circuit may be configured to generate a first pulse train and deliver the first pulse train to a target, and may be configured to generate at least a second pulse train and deliver the at least second pulse train to a target. The safety circuit may be configured to prevent the CEW from applying pulse trains to the target after a predetermined number of pulse trains. The first pulse train may include two or more pulses having waveforms substantially identical with each other, each of the waveforms of the two or more pulses having both a positive voltage segment and a negative voltage segment.

An implantable pulse generator (IPG) is disclosed having an improved ability to steer anodic and cathodic currents between the IPG's electrodes. Each electrode node has at least one PDAC/NDAC pair to source/sink or sink/source a stimulation current to an associated electrode node. Each PDAC and NDAC receives a current with a magnitude indicative of a total anodic and cathodic current, and data indicative of a percentage of that total that each PDAC and NDAC will produce in the patient's tissue at any given time, which activates a number of branches in each PDAC or NDAC. Each PDAC and NDAC may also receive one or more resolution control signals specifying an increment by which the stimulation current may be adjusted at each electrode. The current received by each PDAC and NDAC is generated by a master DAC, and is preferably distributed to the PDACs and NDACs by distribution circuitry.

A method monitors a sensor clock signal in a sensor unit, which is generated and output for a data transfer between the sensor unit and a control unit with a predefined period duration. A reference clock signal having a predefined reference period duration is received. The sensor clock signal is compared to the reference clock signal. Based on the comparison, a deviation of the current period duration of the sensor clock signal from a target period duration is detected. Based on the detected deviation, a counting pulse or a reset pulse is emitted.