The present electronic generator of modulated subcarrier pulse signals includes a module (15) for modulating a pulse train, the position and amplitude of which are controllable, forming a switching signal (S.sub.3); a switching module (16), connected to the output of the module (15) for modulating a pulse train, including at least one transistor (22), controlled by said switching signal (S.sub.3), a voltage-controlled frequency-locking oscillator (18) having a frequency-locking band around a free oscillation frequency controlled by a control voltage, connected to the output of the switching module (16), the switching module making possible the injection of a periodic pulse signal (S.sub.4) having a frequency spectrum including at least one frequency line within said frequency locking band. Such arrangement makes it possible to obtain, at the output of the oscillator, frequency-controlled, phase-controlled and amplitude-controlled modulated subcarrier pulsed signals (S.sub.5).

In described examples, a method of inductive coupled communications includes providing a first resonant tank (first tank) and a second resonant tank (second tank) tuned to essentially the same resonant frequency, each having antenna coils and switches positioned for changing a Q and a bandwidth of their tank. The antenna coils are separated by a distance that provides near-field communications. The first tank is driven to for generating induced oscillations to transmit a predetermined number of carrier frequency cycles providing data. After the predetermined number of cycles, a switch is activated for widening the bandwidth of the first tank. Responsive to the oscillations in the first tank, the second tank begins induced oscillations. Upon detecting a bit associated with the induced oscillations, a switch is activated for widening the bandwidth of the second tank and a receiver circuit receiving an output of the second tank is reset.

A pipelined decimation in frequency FFT butterfly method, and an apparatus to perform this method comprising: a data memory with at least one read port and one write port; an add/subtract unit receiving data from the memory; a multiply/accumulate unit receiving data from the add/subtract unit; a source of coefficients, from logic gates or a coefficient memory, to supply FFT twiddle factors to the multiply/accumulate unit; a shifter receiving data from at least one of the add/subtract unit and the multiply/accumulate unit, the shifter supplying data to the write port of the data memory; wherein the apparatus performs these calculations in four cycles of the add/subtract unit and in four cycles of the multiply/accumulate unit, using complex arithmetic.

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

A system and method is provided including a first pulse width modulation (PWM) generator circuit including a first timer to generate a first cycle count, a first configuration register to define characteristics of a first electrical pulse to be generated, and a trigger cycle count specifying a timing of a first trigger signal, and a first load enable input to load a new configuration value into the first configuration register, a second PWM generator circuit including a second timer to generate a second cycle count, a second configuration register to define characteristics of a second electrical pulse to be generated, a second load enable input to load a new configuration value into the second configuration register, and a load enable selector to selectively drive the second load enable input based on the first trigger signal.

A system and method is provided including a first pulse width modulation (PWM) generator circuit including a first timer to generate a first cycle count, a first configuration register to define characteristics of a first electrical pulse to be generated, and a trigger cycle count specifying a timing of a first trigger signal, and a first load enable input to load a new configuration value into the first configuration register, a second PWM generator circuit including a second timer to generate a second cycle count, a second configuration register to define characteristics of a second electrical pulse to be generated, a second load enable input to load a new configuration value into the second configuration register, and a load enable selector to selectively drive the second load enable input based on the first trigger signal.