An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.

An apparatus for performing a frequency multiplication of an mm-wave wave signal is provided. The apparatus includes a first differential circuit that is capable of receiving a 0 phase component of an input signal and a 180 phase component of the input signal having a first frequency. The first differential circuit provides a first output signal that is twice the frequency and is in phase(0) based on the 0 the 180 phase components of the input signal. The apparatus also includes a second differential circuit that is capable of receiving a 90 phase component of the input signal and a 270 phase component of the input signal, and provide a first output signal that is twice the frequency and out of phase(180). The apparatus also includes a differential transformer that is configured to receive the first output signal and the second output signal. The differential transformer is configured to provide a differential output signal that has a second frequency that is twice the first frequency.

An example of a device for generating a broadband frequency signal comprises a first controlled oscillator, a second controlled oscillator, a phase-locked loop for feeding back an output signal of a controlled oscillator to the corresponding controlled oscillator, and a mixer. The mixer is configured to generate the broadband frequency signal by mixing an output signal of the first controlled oscillator and an output signal of the second controlled oscillator. The device may, for example, be realized by means of a single phase-locked loop. A further example relates to a device for generating a frequency signal with a controlled oscillator and a phase-locked loop with a further controlled oscillator and a mixer in the feedback path of the phase-locked loop. Examples further relate to a high-frequency device for emitting a high-frequency signal and a method for generating a broadband frequency signal.

An apparatus for performing a frequency multiplication of an mm-wave wave signal is provided. The apparatus includes a first differential circuit that is capable of receiving a 0 phase component of an input signal and a 180 phase component of the input signal having a first frequency. The first differential circuit provides a first output signal that is twice the frequency and is in phase(0) based on the 0 the 180 phase components of the input signal. The apparatus also includes a second differential circuit that is capable of receiving a 90 phase component of the input signal and a 270 phase component of the input signal, and provide a first output signal that is twice the frequency and out of phase(180). The apparatus also includes a differential transformer that is configured to receive the first output signal and the second output signal. The differential transformer is configured to provide a differential output signal that has a second frequency that is twice the first frequency.

Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.

An oscillator and method for maintaining a phase lock is provided. The oscillator may include an oscillator input port for receiving a reference signal, an oscillator output port for outputting an oscillator output, an unlocked oscillator oscillating in an unlocked state and outputting at a resonance frequency configured to drift in response to changes in an operating environment, and a phase locked loop (PLL) including a mixer having an output port configured to output the unlocked oscillator output mixed with a local oscillator output, the mixer output port in communication with a phase frequency detector and the oscillator output port, and the phase frequency detector generating a control signal based on a detected phase difference between the reference signal and the mixer output wherein the control signal adjusts the local oscillator output to compensate for the resonance frequency drift of the unlocked oscillator when mixed with the unlocked oscillator output.

Multi-phase clock generation employing phase error detection between multiple delay circuit outputs in a controlled delay line to provide error correction is disclosed. A multi-phase clock generator is provided that includes a controlled delay line and a phase error detector circuit. Tap nodes are provided from outputs of one or more delay circuits in the controlled delay line. To detect and correct for phase errors in the controlled delay line, a phase detection circuit is provided that includes at least two phase detectors each configured to measure a phase offset error between tap nodes from the delay circuit(s) in the controlled delay line. These phase errors are then combined to create an error correction signal, which is used to control the delay of the delay circuit(s) in the controlled delay line to lock the phase of the output of the final delay circuit to an input reference clock signal.

Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.