A positioning method is applied to a terminal device that includes a positioning chip and a system on chip (SoC). The method includes receiving, by the positioning chip, a satellite signal transmitted by at least one satellite, obtaining, by the positioning chip using the SoC, a differential correction value sent by a reference station, and performing, by the positioning chip based on a carrier phase differential technology, positioning calculation using the satellite signal and the differential correction value.

An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

A wide band frequency synthesizer may include a primary phase-locked loop (PLL) to receive a signal that include a local signal and a VCO signal mixed together and to generate the tuning voltage based on a phase comparison of the local signal and the VCO signal. The local signal may be obtained from a reference signal through frequency multiplication. If the primary PLL fails to lock onto an output frequency, a secondary PLL (acquisition circuit) may be switched in performing a phase comparison between the reference signal and the VCO signal to generate the tuning voltage. The secondary PLL may then provide the tuning voltage to an output of the primary PLL.

A method of calibrating an All-Digital Phase Locked Loop (ADPLL) includes obtaining a model of the ADPLL and applying an input signal to both the ADPLL and to the model. The ADPLL generates an actual output of the ADPLL, while the model generates a model output. An error between the actual output of the ADPLL and the model output is then sensed. The method also includes generating a calibration value based on the error between the actual output of the ADPLL and the model output, and adjusting a feedforward gain of the ADPLL based on the calibration value.

The present invention provides a digitally controlled oscillator device capable of realizing a reduction in DNL. The digitally controlled oscillator device includes, for example, an amplifier circuit block, coil elements and a plurality of unitary capacitor units coupled in parallel between oscillation output nodes. Each of the unitary capacitor units is provided with capacitive elements, and a switch which selects whether the capacitive elements should be allowed to contribute as set parameters for an oscillation frequency. The switch is driven by an on/off control line extending from a decoder circuit. The on/off control line is shielded between the oscillation output nodes by a shield section.

A phase coherent synthesizer with good phase noise and spurious performance is described. The phase coherent synthesizer includes digital direct synthesizer (DDS) circuitry, frequency multiplier circuitry, an oscillator, and a mixing stage. The digital direct synthesizer (DDS) circuitry has a first output and a second output. The first output is associated with a fine resolution synthesis. The second output is associated with a step synthesis. A second output signal provided via the second output has a higher frequency compared with a first output signal provided via the first output. The frequency multiplier circuitry is connected with the second output. The frequency multiplier circuitry is configured to multiply the second output signal received via the second output, thereby generating a multiplied output signal. The mixing stage has two input ports connected with the frequency multiplier circuitry and the oscillator respectively. The mixing stage includes, for example, circuitry configured to mix the multiplied output signal and an oscillator output signal of the oscillator, thereby generating an intermediate frequency signal. The first output signal and the intermediate frequency signal are synchronized with each other.

Frequency synthesizers having reduced phase noise and a small step size. One example can provide frequency synthesizers having low phase noise by eliminating dividers in a feedback path and instead employing frequency converters, such as mixers. Step size can be further reduced by providing frequency converters in a reference signal feedforward path. Acquisition time can be decreased by employing a fast-acquisition phase-locked loop that is switched out after acquisition in favor of a low phase-noise phase-locked loop. Another example can reduce phase noise by employing a YIG oscillator. To improve acquisition time, a first, faster phase-locked loop can be used to lock to a signal before switching to a second, slower phase-locked loop that includes the YIG oscillator. Another example can provide low noise by including phase-locked loops that operate in a frequency range having low thermal noise while a frequency of an output signal varies over a wide range.

Frequency synthesizers having reduced phase noise and a small step size. One example can provide frequency synthesizers having low phase noise by eliminating dividers in a feedback path and instead employing frequency converters, such as mixers. Step size can be further reduced by providing frequency converters in a reference signal feedforward path. Acquisition time can be decreased by employing a fast-acquisition phase-locked loop that is switched out after acquisition in favor of a low phase-noise phase-locked loop. Another example can reduce phase noise by employing a YIG oscillator. To improve acquisition time, a first, faster phase-locked loop can be used to lock to a signal before switching to a second, slower phase-locked loop that includes the YIG oscillator. Another example can provide low noise by including phase-locked loops that operate in a frequency range having low thermal noise while a frequency of an output signal varies over a wide range.

An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

An example of a device for generating a broadband frequency signal comprises a first controlled oscillator, a second controlled oscillator, a phase-locked loop for feeding back an output signal of a controlled oscillator to the corresponding controlled oscillator, and a mixer. The mixer is configured to generate the broadband frequency signal by mixing an output signal of the first controlled oscillator and an output signal of the second controlled oscillator. The device may, for example, be realized by means of a single phase-locked loop. A further example relates to a device for generating a frequency signal with a controlled oscillator and a phase-locked loop with a further controlled oscillator and a mixer in the feedback path of the phase-locked loop. Examples further relate to a high-frequency device for emitting a high-frequency signal and a method for generating a broadband frequency signal.