An exemplary system includes a PLL circuit and a precision timing circuit connected to the PLL circuit. The PLL circuit has a PLL feedback period defined by a reference clock and includes a voltage controlled oscillator configured to lock to the reference clock and having a plurality of stages configured to output a plurality of fine phase signals each having a different phase, and a feedback divider configured to be clocked by a single fine phase signal included in the plurality of fine phase signals and have a plurality of feedback divider states during the PLL feedback period. The precision timing circuit is configured to generate a timing pulse and set, based on a first combination of one of the fine phase signals and one of the feedback divider states, a temporal position of the timing pulse within the PLL feedback period.

An exemplary system includes a PLL circuit and a precision timing circuit connected to the PLL circuit. The PLL circuit has a PLL feedback period defined by a reference clock and includes a voltage controlled oscillator configured to lock to the reference clock and having a plurality of stages configured to output a plurality of fine phase signals each having a different phase, and a feedback divider configured to be clocked by a single fine phase signal included in the plurality of fine phase signals and have a plurality of feedback divider states during the PLL feedback period. The precision timing circuit is configured to generate a timing pulse and set, based on a first combination of one of the fine phase signals and one of the feedback divider states, a temporal position of the timing pulse within the PLL feedback period.

A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

A digital phase-locked loop (DPLL) may include a time-to-digital converter (TDC) to provide a phase error signal, a frequency-divider to perform frequency division on an output signal to generate a frequency-divided output signal, a delta-sigma-modulator (DSM) to provide a test signal that represents a quantization error of the DSM, and a digital-to-time converter (DTC) to at least partially remove the quantization error from the frequency-divided output signal based on the test signal to generate the feedback signal. The DPLL may include a circuit to cause the DTC to provide a percentage of the quantization error such that the percentage of the quantization error is in the phase error signal, and a TDC calibration component to calibrate the TDC by applying a gain adjustment factor to the TDC. The gain adjustment factor may be based on the test signal and the phase error signal including the percentage of the quantization error.

A digital phase-locked loop (DPLL) may include a time-to-digital converter (TDC) to provide a phase error signal, a frequency-divider to perform frequency division on an output signal to generate a frequency-divided output signal, a delta-sigma-modulator (DSM) to provide a test signal that represents a quantization error of the DSM, and a digital-to-time converter (DTC) to at least partially remove the quantization error from the frequency-divided output signal based on the test signal to generate the feedback signal. The DPLL may include a circuit to cause the DTC to provide a percentage of the quantization error such that the percentage of the quantization error is in the phase error signal, and a TDC calibration component to calibrate the TDC by applying a gain adjustment factor to the TDC. The gain adjustment factor may be based on the test signal and the phase error signal including the percentage of the quantization error.

According to an exemplary embodiment of the present disclosure, a fractional-N sub-sampling phase locked loop using a phase rotator includes a frequency locked loop which is locked at a fractional-N frequency using a delta-signal modulator and a sub-sampling phase locked loop which locks a phase to a fractional multiple using a phase rotator, and the phase rotator applies a fractional multiple to a phase of a signal output from the oscillator.

The present invention provides a transceiver circuit including a transmitter circuit, a frequency synthesizer and control circuit. The transmitter circuit is configured to generate a transmission signal, wherein the transmission signal is transmitted through an antenna. The frequency synthesizer is configured to generate a clock signal for the transmitter circuit to generate the transmission signal. The control circuit is configured to generate a first control signal to control the frequency synthesizer to determine a loop bandwidth of the frequency synthesizer; wherein when the transceiver circuit operates in a standby mode, the control circuit generates the first control signal to make the frequency synthesizer have a first loop bandwidth; and after a period of time after the transceiver circuit is switched from the standby mode to a transmission mode, the control circuit generates the first control signal to make the frequency synthesizer have a second loop bandwidth.

The present invention provides a transceiver circuit including a transmitter circuit, a frequency synthesizer and control circuit. The transmitter circuit is configured to generate a transmission signal, wherein the transmission signal is transmitted through an antenna. The frequency synthesizer is configured to generate a clock signal for the transmitter circuit to generate the transmission signal. The control circuit is configured to generate a first control signal to control the frequency synthesizer to determine a loop bandwidth of the frequency synthesizer; wherein when the transceiver circuit operates in a standby mode, the control circuit generates the first control signal to make the frequency synthesizer have a first loop bandwidth; and after a period of time after the transceiver circuit is switched from the standby mode to a transmission mode, the control circuit generates the first control signal to make the frequency synthesizer have a second loop bandwidth.

The present disclosure discloses an on-chip synchronous self-repairing system based on a low-frequency reference signal. The system adopts a dual-input PLL stellate coupled structure or a dual-input PLL butterfly-shaped coupled structure, and delay of the whole loop is made to be an integral multiple of the reference signal by synchronizing the transmitted reference signal with the received reference signal, so as to ensure synchronization of local oscillation signal of each IC chip. The transmission wire based on an adjustable left-handed material is used as a delay wire to connect the dual-input PLL, thereby achieving low loss and reducing the physical distance of the delay wire. The system has the advantages of small area, low loss, strong adaptability and strict synchronization in various environments.