A frequency-to-digital-converter based PLL (FDC-PLL) that implements the functionality of a charge pump and analog-to-digital converter (ADC) with a dual-mode ring oscillator (DMRO) and digital logic. Preferred embodiments of the invention include circuit-level techniques that provide better spurious tone performance and very low phase noise with lower power dissipation and supply voltage than prior digital PLLs known to the inventors

A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.

One example of a radar device includes a phase-locked loop for generating a radiofrequency signal. The phase-locked loop has a multi-modulus divider. The radar device furthermore comprises a delta-sigma modulator for generating a modulated signal for the multi-modulus divider, and a signal generator for generating an input signal for the delta-sigma modulator. The radar device has monitoring circuits, wherein a first monitoring circuit is configured to monitor a locked state of the phase-locked loop, a second monitoring circuit is configured to monitor the delta-sigma modulator, and a third monitoring circuit is configured to monitor the signal generator.

An apparatus is disclosed that implements phase-locked loop (PLL) calibration. In an example aspect, the apparatus includes a PLL and a signal extraction path. The PLL includes an error determiner with an error output node and a loop filter with a filter input node and a filter output node. The filter input node is coupled to the error output node. The PLL also includes a voltage-controlled oscillator (VCO) with a VCO input node. The VCO input node is coupled to the filter output node. The PLL further includes a PLL tap node coupled between the filter output node and the VCO input node. The signal extraction path includes at least one switch, with the signal extraction path coupled to the PLL tap node.

A DTC circuit, includes: a DAC connected to a first node; a first switch connected between a first power source and a second node, and to provide a charge current to the second node according to a first switching signal; and a second switch connected between the first node and the second node, and to electrically connect the DAC to the second node according to a second switching signal. The DAC is to be charged to generate a voltage ramp corresponding to the charge current during a first DTC operational phase when the first and second switching signals have an active level to turn on the first and second switches, and to generate an input control word dependent voltage according to an input control word during a second DTC operational phase when the first and second switching signals have an inactive level to turn off the first and second switches.

An element includes a coupling line in which a first conductor layer, a dielectric layer, and a second conductor layer are stacked in this order, and which is connected to the second conductor layer in order to mutually synchronize a plurality of antennas at a frequency of a terahertz wave; and a bias line connecting a power supply for supplying a bias signal to a semiconductor layer and the second conductor layer. A wiring layer in which the coupling line is formed and a wiring layer in which the bias line is formed are different layers. The bias line is disposed in a layer between the first conductor layer and the second conductor layer.

A hybrid true single-phase clock (H-TSPC) circuit includes a first logic circuit comprising non-ratio (NR) logic, a first mode switching device coupled to an output of the first logic circuit, a second logic circuit comprising ratio (R) logic, the second logic circuit configured to receive an output of the first logic circuit, a second mode switching device coupled to an output of the second logic circuit, a third logic circuit comprising non-ratio (NR) logic, the third logic circuit configured to receive an output of the second logic circuit, and a third mode switching device coupled to an output of the third logic circuit, wherein the first logic circuit, second logic circuit, and third logic circuit are configured in a ring.

Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time in response to the input clock; and outputs a second clock from an output of one of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another, each stage includes two PMOS FETs and an NMOS FET.

A circuit includes a clock generator, a frequency divider, and a first biasing circuit. The clock generator generates a clock signal of a first frequency. The frequency divider includes a first pair of cross coupled transistors. The frequency divider produces the clock signal of a second frequency. The first biasing circuit is coupled with the first pair of cross coupled transistors of the frequency divider. The first biasing circuit is adapted to enable a change in a transconductance of the first pair of cross coupled transistors to stabilize a phase angle between the clock signal at the first frequency and the clock signal at the second frequency.

A circuit includes a clock generator, a frequency divider, and a first biasing circuit. The clock generator generates a clock signal of a first frequency. The frequency divider includes a first pair of cross coupled transistors. The frequency divider produces the clock signal of a second frequency. The first biasing circuit is coupled with the first pair of cross coupled transistors of the frequency divider. The first biasing circuit is adapted to enable a change in a transconductance of the first pair of cross coupled transistors to stabilize a phase angle between the clock signal at the first frequency and the clock signal at the second frequency.