Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.

Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.

Methods and apparatus for synchronizing data transfers across clock domains for using heads-up indications. An integrated circuit includes a first-in first-out buffer (FIFO); a memory controller configured to operate in a first clock domain and coupled to the FIFO, the first clock domain associated with a first clock signal; a data fabric configured to operate in a second clock domain and coupled to the FIFO, the second clock domain associated with a second clock signal, a second frequency of the second clock signal being different from a first frequency of the first clock signal; and a controller coupled to the FIFO. In some instances, the controller determines a phase relationship between the first clock signal and the second clock signal; monitors one or more first clock edges of the first clock signal and one or more second clock edges of the second clock signal; and sends a first heads-up signal to the memory controller.

Methods and apparatus for synchronizing data transfers across clock domains for using heads-up indications. An integrated circuit includes a first-in first-out buffer (FIFO); a memory controller configured to operate in a first clock domain and coupled to the FIFO, the first clock domain associated with a first clock signal; a data fabric configured to operate in a second clock domain and coupled to the FIFO, the second clock domain associated with a second clock signal, a second frequency of the second clock signal being different from a first frequency of the first clock signal; and a controller coupled to the FIFO. In some instances, the controller determines a phase relationship between the first clock signal and the second clock signal; monitors one or more first clock edges of the first clock signal and one or more second clock edges of the second clock signal; and sends a first heads-up signal to the memory controller.

A time-synchronization apparatus and/or method involves identifying a frequency offset by implementing a frequency-offset-acquisition process which includes counting cycles of a local clock signal within a period of a reference pulse train. A phase offset of the local clock signal is determined, a residual frequency error is generated based on the phase offset, and at least one timer-adjustment signal that is based on the frequency offset and the residual frequency error is provided.

A time-synchronization apparatus and/or method involves identifying a frequency offset by implementing a frequency-offset-acquisition process which includes counting cycles of a local clock signal within a period of a reference pulse train. A phase offset of the local clock signal is determined, a residual frequency error is generated based on the phase offset, and at least one timer-adjustment signal that is based on the frequency offset and the residual frequency error is provided.

This disclosure is directed to enhancing PLL performance via gain calibration and duty cycle calibration. It may be desirable to perform loop gain and duty cycle calibration simultaneously. However, doing so may result in prohibitive complexity and/or area/power penalty. To enable loop gain calibration and duty cycle calibration simultaneously, the duty cycle error and the gain error may be detected in the time domain, which may enable duty cycle calibration and loop gain calibration circuitries to share a phase detector. Detecting the duty cycle error and the loop gain error in the time domain may be accomplished by implementing an analog or digital PLL system, wherein the loop gain of the PLL system is a function of the input phase offset time.

This disclosure is directed to enhancing PLL performance via gain calibration and duty cycle calibration. It may be desirable to perform loop gain and duty cycle calibration simultaneously. However, doing so may result in prohibitive complexity and/or area/power penalty. To enable loop gain calibration and duty cycle calibration simultaneously, the duty cycle error and the gain error may be detected in the time domain, which may enable duty cycle calibration and loop gain calibration circuitries to share a phase detector. Detecting the duty cycle error and the loop gain error in the time domain may be accomplished by implementing an analog or digital PLL system, wherein the loop gain of the PLL system is a function of the input phase offset time.

This disclosure is directed to PLLs, and, in particular, to enhancing PLL performance via gain calibration. PLL loop gain may vary with respect to process, voltage, and temperature (PVT) variation. To control the PLL loop gain, a gain calibration loop may be implemented. However, calibrating the loop gain by directly measuring the loop gain may be disadvantageous. To reduce or eliminate PLL loop gain variation due to PVT variation, a PLL having a loop gain function that is a function of an input phase offset time with a phase noise performance that remains consistent across PVT variations is disclosed. By determining a relationship between PLL loop gain and phase offset, detecting and calibrating phase offset may result in enhanced calibration of the PLL loop gain, while avoiding the additional difficulty and complexity associated with directly measuring loop gain of a PLL.

This disclosure is directed to PLLs, and, in particular, to enhancing PLL performance via gain calibration. PLL loop gain may vary with respect to process, voltage, and temperature (PVT) variation. To control the PLL loop gain, a gain calibration loop may be implemented. However, calibrating the loop gain by directly measuring the loop gain may be disadvantageous. To reduce or eliminate PLL loop gain variation due to PVT variation, a PLL having a loop gain function that is a function of an input phase offset time with a phase noise performance that remains consistent across PVT variations is disclosed. By determining a relationship between PLL loop gain and phase offset, detecting and calibrating phase offset may result in enhanced calibration of the PLL loop gain, while avoiding the additional difficulty and complexity associated with directly measuring loop gain of a PLL.