An oscillator includes a first resonator element, a circuit element configured to oscillate the first resonator element to generate an oscillation signal, a first package which includes a substrate, and has a housing space configured to house the first resonator element and the circuit element at one principal surface side of the substrate, a second resonator element which is disposed at another principal surface side of the substrate, and an oscillation frequency of which is controlled based on the oscillation signal, and a leg part which is disposed at the another principal surface side of the substrate, and which is arranged so as to surround the second resonator element in a plan view of the substrate.

A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the up/down control signals. The integral signal component control signal and proportional signal component control signal are separate control signals. A voltage controlled oscillator generates an oscillating output signal having a frequency controlled by the integral signal component control signal and the proportional signal component control signal. A divider circuit performs a frequency division on the oscillating output signal to generate the feedback clock signal.

Embodiments herein relate to a phase-locked loop (PLL) circuit which compensates for varying delays in a feedback clock signal which are caused by the use of fractional division. In one aspect, a delay circuit is used to provide progressively larger delays for the feedback clock signal within each division cycle, when the divider uses the smaller divisor, N. This compensates for the associated larger frequency and smaller clock cycle, compared to when the divisor is N+1. Additionally, the delays introduced by the delay circuit can be controlled by an adaptive gain circuit. The adaptive gain circuit samples a phase error of a phase detector of the PLL to determine whether to increase or decreases the gain, thereby increasing or decreasing, respectively, the delay.

Embodiments included herein are directed towards a fractional feedback divider circuit and associated method. The circuit may include a programmable feedback divider including a plurality of flip-flops arranged in series. The programmable feedback divider may be configured to receive an input clock signal and a reset signal comprising at least one pulse and to generate a divided clock. The circuit may include reset logic configured to receive an input from the programmable feedback divider and to generate a reset signal. The circuit may include a first D flip-flop configured to receive the reset signal and to generate an output and a second D flip-flop configured to receive the output from the first D flip-flop and to generate a second output. The circuit may further include a multiplexer configured to receive the second output and to generate an output clock signal.

In a wireless power transmitting device, a control circuit outputs a control signal for setting a frequency and a phase of an F-PLL signal generated by an F-PLL, the F-PLL generates the F-PLL signal having the frequency and the phase set by the control signal output from the control circuit, and a frequency conversion circuit generates a transmission signal by converting a frequency of the F-PLL signal generated by the F-PLL.

A SerDes module clock network architecture comprises, a reference clock input port, a plurality of data transmission channels, several user logic interfaces, several frequency division branches and a phase locked loop. The reference lock input port receives an input clock and conveys the input clock to the phase locked loop, the phase locked loop receives the input lock and outputs a PLL output clock signal, the PLL output clock signal is conveyed to the plurality of data transmission channels, and the PLL output clock signal is conveyed to the frequency division branches, and after frequency division, user interface clocks are output and conveyed to the user logic interfaces. When the PLL output clock signal in a SerDes is provided to an internal dedicated channel, several frequency division branches are also divided, and after frequency division, the signal is output to the user logic interfaces for use by an FPGA.

A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (ΔΦ.sub.LO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.

Disclosed is a frequency dividing circuit, a frequency dividing method and a phase locked loop. The frequency dividing circuit comprises: a clock selection unit outputting a first clock signal, select a second clock signal lagging behind the first clock signal by (½-1/M) of one phase; an integer frequency dividing unit performing frequency division on the first clock signal to provide a frequency-divided clock signal; a trigger unit triggering the frequency-divided clock signal according to the second clock signal to obtain a modulation clock signal; a switching signal unit providing a switching signal according to the modulation clock signal and a preset target output frequency. The clock selection unit selects and further outputs a third clock signal as the first clock signal according to the target phase selection information, to adjust the frequency of the frequency-divided clock signal, reduce noise and improve loop bandwidth of the phase locked loop.

In a communication system of the LPWAN type including a server and a plurality of gateways intended to make wireless communications with terminals in said communication system, the server: obtains a description of a mobility hierarchy in which mobility types are hierarchically defined; obtains a description of a mobility tree in which mobility areas are hierarchically defined, in conformity with the mobility hierarchy; obtains terrain measurements associated with each mobility area defined in the mobility tree; establishes a frequency plan on the basis of the mobility tree and terrain measurements; and configures the gateways and the terminals according to the frequency plan established.

A programmable frequency divider includes a modulus frequency divider, a pulse counter, and a swallow counter. The pulse counter is configured to count an output signal from the modulus frequency divider, and output a frequency division signal, and the swallow counter is configured to count the output signal from the modulus frequency divider and perform resetting on the basis of the frequency division signal from the pulse counter, the programmable frequency divider being configured to control the modulus frequency divider on the basis of a signal from the swallow counter. The programmable frequency divider includes a control signal delay circuit, disposed between an output terminal of the swallow counter and a control terminal of the modulus frequency divider, configured to delay a signal from the swallow counter, and generate a control signal for controlling the modulus frequency divider.