A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.

An analog-to-digital conversion circuit includes a comparator circuit configured to perform processing of comparison between an analog signal and a ramp signal, and a counter configured to perform count processing in parallel with the comparison processing by the comparator circuit. The analog-to-digital conversion circuit acquires digital data, which is a count value corresponding to the comparison processing, and subjects the analog signal to analog-to-digital conversion. A period from the start to the end of the analog-to-digital conversion of the one analog signal includes a first period and a second period following the first period. The first and the second periods are switched based on an output of the counter. The count processing is performed at a high speed during the first period and performed at a low speed during the second period.

A method and a device for matching a quantization table of data representative of a radio signal received by a radio antenna of a mobile network. The method includes: obtaining an item of information representative of a channel decoding error rate of a decoded quantized demodulated signal from a demodulation of the radio signal received by the antenna, the demodulated radio signal having been quantized by the quantization table, and the quantized demodulated radio signal having undergone a channel decoding; matching the quantization table when the channel decoding error rate is higher than a determined threshold; and transmitting an item of information representative of the matching of the quantization table to a channel decoding device or to a demodulation device.

Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.

An analog-to-digital converter that converts an inputted analog signal into a digital value is disclosed that may include unit circuits that each generate reference voltages comprising regular potential intervals by a series resistor circuit connected between a high potential side reference voltage and a low potential side reference voltage and convert the reference voltages into a digital value by comparing the reference voltages with the inputted analog signal, and an adder that adds the digital values converted by the unit circuits. Each unit circuit may include coupling switches that couple the series resistor circuit with the series resistor circuit of another one of the unit circuits and connect the series resistor circuits between the high potential side reference voltage and the low potential side reference voltage and a sharing switch that shares the inputted analog signal with the other unit circuit that is coupled with the series resistor circuit.

A digital-to-analog converter device including a set of components, each component included in the set of components including a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell is provided by the present disclosure. The digital-to-analog converter device further includes a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches. The digital-to-analog converter device is configured to output an output signal at the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components.

Methods, systems, and devices for wireless communication are described for one or more aspects of dynamically configuring an analog-to-digital converter (ADC). A user equipment (UE) may determine a set of supported ADC resolution sizes including one or more dynamically configurable bit quantities. The UE may transmit a capability message including an indication of the set of ADC resolution sizes to a base station. The UE may indicate, to the base station, a power consumption factor or a table of signal-to-quantization noise ratios (SQNR) per bit quantity supported by the UE's ADC. In some cases, the base station may enable, based on the set of ADC resolution sizes, clipping of a power amplifier and one or more associated precoding parameters, and may indicate the precoding parameters to the UE. The UE may select an ADC resolution size for processing received messages.

A method for quantizing data representative of a radio signal received by a radio antenna of a mobile network. The method includes: demodulating the radio signal received by the antenna, providing a demodulated signal; scalar quantizing each value of the demodulated signal using a quantization table selected according to a channel coding level used to transmit the radio signal, providing a quantized demodulated signal; and transmitting the quantized demodulated signal to a channel decoding module.

An analog-to-digital conversion circuit includes a comparator circuit configured to perform processing of comparison between an analog signal and a ramp signal, and a counter configured to perform count processing in parallel with the comparison processing by the comparator circuit. The analog-to-digital conversion circuit acquires digital data, which is a count value corresponding to the comparison processing, and subjects the analog signal to analog-to-digital conversion. A period from the start to the end of the analog-to-digital conversion of the one analog signal includes a first period and a second period following the first period. The first and the second periods are switched based on an output of the counter. The count processing is performed at a high speed during the first period and performed at a low speed during the second period.