A comparator including: first and second input transistors connected to control signals at first and second nodes of the comparator; latch circuitry; at least one controllable offset-correction component having an input terminal and connected to control the signal at one of the first and second nodes based on an offset-correction signal provided at its input terminal; for each controllable offset-correction component, an offset correction circuit configured to provide the offset-correction signal provided at its input terminal; and control circuitry. The control circuitry controls the at least one offset-correction circuit to: control an amount by which the offset-correction signal is adjusted; and/or in a bypass operation, connect the input terminal of the at least one controllable offset-correction component to a bypass-operation reference voltage supply; and/or in a maintenance operation, control the charging-operation voltage supply and/or the bypass-operation voltage supply to control leakage of the charge stored on the holding capacitor.

A switched-capacitor amplifier comprises a comparator, sample and amplification capacitors and a controller to control charge and discharge current sources in dependence on an output signal of the comparator. A closed loop control circuit is configured to determine the delay of the comparator and control an offset of the comparator in response to the determined delay.

The invention relates to a method for synchronizing a plurality of analogue-digital or digital-analogue converters (CONV_k), the converters (CONV_k) all being connected to a control unit (UC), and to a clock (CLK) that has a predefined clock period (T.sub.clk), the converters being also chained step-by-step so as to form a chain of converters, each converter (CONV_k) generating an internal synchronization signal (internal_sync_k) configured to supply a time reference on the transmission of data by the converter (CONV_k).

The method allows the synchronization of the converters to be guaranteed using a process of learning and of configuration of the converters. The method allows any line distance constraint on the synchronization signal to be overcome.

A device includes a first compensation circuit configured to adjust an analog front end (AFE) output to generate a first adjusted AFE output, a first data slicer configured to output a first voltage based on the first adjusted AFE output. The first compensation circuit includes a first path between a voltage source and a ground, including a first transistor, a first adjustable current source, a first input voltage node configured to receive the AFE output, and a first output voltage node coupled to the first data slicer, a second path between the voltage source and the ground, including a second transistor, a second adjustable current source, a second input voltage node configured to receive the AFE output, and a second output voltage node coupled to the second data slicer, and a configurable resistance resistor and a configurable capacitance capacitor coupled in parallel across the first path and the second path.

Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.

An A/D conversion circuit includes a comparison-reference-signal generator section configured to generate a comparison reference signal synchronized with a sampling clock signal, a comparator configured to compare a voltage of an input signal and a voltage of the comparison reference signal to thereby generate a trigger signal, a time to digital converter configured to calculate a first time digital value, and a digital-signal generator section configured to generate, based on the first time digital value and a second time digital value, a digital signal corresponding to the voltage of the input signal. The first time to digital converter includes a state transition section configured to start transition of a state based on the trigger signal and output state information, and a weight operation section configured to, in synchronization with the reference clock signal, perform, on a value based on the state information, weighting corresponding to time elapsing and perform a predetermined arithmetic operation to thereby calculate the first time digital value corresponding to the number of transition times of the state.

An optical light sensing device includes a detector operable to detect a light wave. The optical light sensing device also includes an integration circuit that includes an operational amplifier that is operable to reduce or cancel dark currents generated at the detector.

An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.

An analog-to-digital converting circuit includes: an analog-to-digital converter suitable for performing an analog-to-digital conversion on pixel signals of a plurality of pixels provided in a pixel array; a ramp signal generator suitable for providing a ramp signal to the analog-to-digital converter; and an auto-zero controller suitable for providing a reference voltage to the analog-to-digital converter to perform an auto-zeroing operation by using a row pixel for which a readout operation is performed by the analog-to-digital converter.

A sample-and-hold amplification circuit can include a sampling circuit configured to sample first and second input signals in response to first and second control signals to generate first and second sampled signals, an amplification circuit configured to amplify a voltage difference between the first and second sampled signals to generate first and second output signals, and an offset compensation circuit configured to form a first path between input and output terminals of the amplification circuit in response to the first control signal to store an offset of the input terminal and form a second path between the input and output terminals in response to the second control signal to reflect the offset to the output terminal.