Technologies directed to a receiver circuit with selective time-interleaved analog-to-digital converters (ADCs) are described. The receiver circuit includes a first ADC, a second ADC, and a digital processing circuit coupled to the first ADC and second ADC that operates in a first mode or a second mode. In the first mode the first ADC receives a first signal and generates first samples at a first sampling frequency. The digital processing circuit processes the first samples. In the second mode, the first ADC and the second ADC both receive a second signal and collectively generate second samples at a second sampling frequency that is greater than the first sampling frequency. The digital processing circuit processes the second samples.

There is described a hybrid ADC device for converting an analog input signal (Vin) into a digital output signal (Vout), the device comprising a first ADC circuit configured to receive the analog input signal (Vin) and convert it into a first digital signal (Y0); a DAC circuit configured to receive the first digital signal and convert it into a first analog signal; a delay circuit configured to delay the analog input signal; a first combiner configured to generate an analog residual signal by subtracting the first analog signal from the delayed analog input signal; a second ADC circuit configured to receive the residual analog signal and convert it into a second digital signal (Y1); a filter circuit configured to receive the first digital signal and output a filtered first digital signal (Y0′), the filter circuit having a transfer function corresponding to a combined transfer function of the DAC circuit and the second ADC circuit; and a second combiner configured to generate the digital output signal (Vout) by adding the second digital signal and the filtered first digital signal, wherein the first ADC circuit comprises an anti-aliasing filter. Furthermore, a corresponding method and an automobile radar system are described.

A signal processing system may include a signal path and a chop management circuit. The signal path may comprise a chopper configured to chop a differential input signal to the signal path at a chopping frequency and a low-pass filter downstream of the chopper and configured to filter out intermodulation products of a direct current offset of the signal path and intermodulation products of an aggressor on the differential input signal in order to generate an output signal. The chop management circuit may be communicatively coupled to the chopper and configured to, based on operational parameters associated with the signal path, dynamically manage energy of one or more clock signals used to define the chopping frequency.

A system and method for calibrating a time-interleaved digital-to-analog converter (DAC). A calibration signal generator generates calibration data, and a time-interleaved DAC converts the calibration data to an analog calibration signal. An observation analog-to-digital converter (ADC) samples, and quantizes, the analog calibration signal filtered by an anti-alias filter. A mismatch estimation block estimates a frequency response mismatch between the sub-DACs and generates a sub-DAC mismatch correction factor based on an output of the observation ADC. The calibration signal generator applies the sub-DAC mismatch correction factor to the calibration data. The mismatch estimation block may estimate a DC offset mismatch between the sub-DACs based on the output of the observation ADC and generates a DC offset correction factor, and the calibration signal generator applies the DC offset correction factor to the calibration data.

A system includes a control circuit and an adjustable low-pass filter. The control circuit is configured to receive an input signal and to control at least one engine output based on the input signal. The adjustable low-pass filter receives the input signal, and filters the input signal prior to forwarding the input signal to the control circuit. The adjustable low-pass filter has a first setting in which the adjustable low-pass filter has a first cut-off frequency and a second setting in which the adjustable low-pass filter has a second cut-off frequency. The first setting configures the control circuit to be used with a first sensor having a first dynamic range and the second setting configures the control circuit to be used with a second sensor having a second dynamic range.

An analog-to-digital conversion system. A clock generator generates a first clock signal at a first frequency. An analog-to-digital converter (ADC) converts an input analog signal to a digital signal. The ADC operates based on the first clock signal at the first frequency. A calibration digital-to-analog converter (DAC) generates an analog reference signal from digital reference data. A fractional rate clock generator generates a second clock signal from the first clock signal. The second clock signal is at a second frequency that is a fractional rate of the first frequency, and the calibration DAC operates at the second frequency. An equalizer processes an output of the ADC to remove a distortion incurred by the ADC and a calibration circuitry generates coefficients for the equalizer based on the digital reference data and the output of the ADC to the analog reference signal.

A controllable opto-electronic time stretcher comprising a first wave guide and a second waveguide coupled to the first waveguide along a coupling portion; wherein at least one of the first and second waveguides in the coupling portion has a controllable refractive index.

Methods, systems, computer-readable media, and apparatuses for spurious information reduction in a data signal are presented. One example of such an apparatus includes a data converter including a plurality of analog-to-digital converters (ADCs) and configured to produce a plurality of sampled signals, a normalizer configured to obtain a plurality of common-bandwidth signals from at least the plurality of sampled signals, and a common-mode filter configured to produce a digital output signal based on the plurality of common-bandwidth signals.

A method of detecting an obtruding signal in a radio receiver, a receiver and a computer program are disclosed. The receiver has a mixer arranged to mix a received signal to an analog baseband signal at or close to zero-frequency, a filter arranged to low-pass filter said analog baseband signal, and an analog-to-digital converter arranged to sample said filtered analog baseband signal at a sample frequency such that a digital baseband signal is formed. The method comprised receiving a radio frequency signal, mixing the radio frequency signal to the analog baseband signal at or close to zero-frequency, low-pass filtering said analog baseband signal, and analog-to-digital converting said filtered analog baseband signal at an over sample frequency such that a digital baseband signal is formed. The method further comprises frequency translating the digital baseband signal around a Nyquist frequency being based on a nominal sample frequency, the nominal sample frequency being a fraction of the oversampling frequency according to the oversampling rate, to form a translated digital baseband signal such that signal content of the digital baseband signal around zero frequency will be translated to around the nominal sample frequency and vice versa in the translated digital baseband signal, determining a first signal level at zero frequency of the digital baseband signal and a second signal level at zero frequency of the translated digital baseband signal, detecting an obtruding signal based on a relation between the first and second signal levels, and outputting an obtruding signal state signal.

An engine control module comprises an input terminal configured to receive an input signal, an analog-to-digital converter configured to receive the input signal from the input terminal, control circuitry configured to receive the input signal from the analog-to-digital converter and to control at least one engine output based on the input signal, and an adjustable low-pass filter. The adjustable low-pass filter is coupled between the input terminal and the analog-to-digital converter such that the analog-to-digital converter receives the input signal from the input terminal via the adjustable low-pass filter. The adjustable low-pass filter is configured to filter the input signal from the input terminal prior to the input signal being applied to the analog-to-digital converter. The adjustable low-pass filter has a first setting in which the adjustable low-pass filter has a first cut-off frequency and a second setting in which the adjustable low-pass filter has a second cut-off frequency, wherein the first setting configures the engine control module to be used with a first sensor having a first dynamic range and the second setting configures the engine control module to be used with a second sensor having a second dynamic range.