A time-interleaved analog-to-digital converter (ADC) uses M analog-to-digital converters to sample an analog input signal to produce digital outputs. The M ADCs, operating in a time-interleaved fashion, can increase the sampling speed several times compared to the sampling speed of just one ADC. The time-interleaved ADC can be programmed and reconfigured to trade one performance metric for another. For example, more time can be given to comparator to improve bit error rate or more time can be given to an amplifier for improved settling which improves SNR, SFDR etc. If the time-interleaved converters are randomized, then the amount of ‘color’ in the noise floor shape can also be traded for other performance metrics.

A method and apparatus for processing a periodic analog signal using a composite ADC including a time interleaved set of sub-ADCs, to produce a replica signal representative of the analog signal, wherein the replica signal is characterized by suppression of additive noise on the periodic analog signal, and correction of sub-ADC-caused distortions. Streams of samples from the respective sub-ADCs are accumulated separately for respective positions in signal periods of the periodic analog signal to provide sub-replicas. Fourier transforms of the replicas are determined for the different sub-ADCs, and those Fourier transforms are averaged to obtain a mean Fourier transform. Frequency responses of the sub-ADCs are corrected by dividing the mean Fourier transform by the respective sub-ADC frequency responses. An averaged replica of the signal period is obtained by determining an inverse Fourier transform of the corrected mean Fourier transform.

In an image pickup device, in a period for which a signal value of the comparison result signal is changed in a certain AD converter among a plurality of AD converters, the signal value of the comparison result signal changes a plurality of times in another AD converter.

A cyclic analog to digital converter for digitizing an output from a photoplethysmography sensor has a buffer amplifier for setting a voltage of the feedback capacitance. Additionally, digital averaging circuit is preferably provided for averaging the digital output from the cyclic analog to digital converter for the several conversions. Finally, voting logic is additionally provided for declaring the digital bits based on successive comparisons by the one or more comparators.

A measurement unit comprising a converter unit and a processing unit is configured to provide a measurement result value, based on a first input signal and a second input signal.

The converter unit is configured to provide a first digital, quantized values based on the first input signal or derived from the first input signal and the second input signal. The converter unit is further configured to provide second digital, quantized values based on the second input signal. The measurement unit is configured to change the one or more control signals of the converter unit between determination of different first values or a determination of the different second values, wherein different first values and/or different second values are provided using different converter quantization step sizes. The processing unit is configured to provide a measurement result value from a predefined number of first values and a predefined number of second values.

A measurement unit comprising a converter unit and a processing unit and configured to provide a measurement result value, based on a first input signal. The converter unit is configured to provide first digital, quantized values based on the first input signal. The measurement unit is further configured to calculate second values, which represents a reference quantity or a reference value, for a plurality of quantization step sizes associated with different values of the control signal. The measurement unit is configured to change the control signal of the converter unit between determination of different first values and/or a determination of the different second values, such that different first values and/or different second values are provided using different converter quantization step sizes. The processing unit is configured to provide a measurement result value from a predefined number of first values and a predefined number of second values.

Repetitive waveforms are processed to produce an averaged replica of the waveforms by first determining a stream of digital samples, with random time shifts of waveform starts relative to the samples. A mutual arrangement of a trigger signal and a following sample over a succession of sampling periods, enables k sections coinciding with segments [k.Math.T/K, (k+1).Math.T/K]. K is determined and a distance D between the trigger signal and the following sample is calculated. Second, values of the samples are transformed so that waveforms represented by the samples, are shifted in time by D in relation to the sample positions. The mutual positions of the delayed waveforms and the sampling clock along multiple axes, exactly repeats so that values of the produced samples along the axes coincide. The discreet time delays before averaging avoid frequency component distortions in resulting replicas of the waveforms.

An error compensation correction device for a pipeline analog-to-digital converter includes a correction pipeline stage and a conventional pipeline stage. For each correction pipeline stage, a corresponding error estimation circuit, a level edge detection circuit, a random level generation circuit, and MUX circuit being provided. The present disclosure can track and correct non-ideal properties and mismatching errors in real time over time along with the change of the surroundings without interrupting the ADC normal work of the pipeline. Thus the correction value is closer to the real situation.

An analog-to-digital converter (ADC) and a method are disclosed. The ADC has a quantizer. The quantizer comprises a linear-feedback shift register (LFSR), a decoder configured to provide a plurality of switch control signals at a plurality of decoder outputs, respectively, the plurality of switch control signals responsive to a LFSR value of the LFSR output; an electrical reference, the electrical reference having a plurality of reference outputs, the electrical reference configured to provide a plurality of reference levels at the plurality of reference outputs, respectively; a first switch providing a first switch output and a second switch output; and a comparator, the comparator having a signal input, a first reference input, and a second reference input, the first reference input connected to the first switch output, and the second reference input connected to the second switch output.

An error compensation correction device for a pipeline analog-to-digital converter includes a correction pipeline stage and a conventional pipeline stage. For each correction pipeline stage, a corresponding error estimation circuit, a level edge detection circuit, a random level generation circuit, and MUX circuit being provided. The present disclosure can track and correct non-ideal properties and mismatching errors in real time over time along with the change of the surroundings without interrupting the ADC normal work of the pipeline. Thus the correction value is closer to the real situation.